M52S128168A-7.5BG ELITE SEMICONDUCTOR, M52S128168A-7.5BG Datasheet - Page 29

• Manufacturer Part Number: M52S128168A-7.5BG
• Description: DRAM IC
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5BG

• Ic Interface Type: Parallel
• Frequency: 133MHz
• Termination Type: SMD
• Supply Voltage Max: 2.7V
• Memory Voltage, Vcc: 2.5 V
• Interface Type: Parallel
• Memory Size: 128Mbit
• Supply Voltage Min: 2.3V
• Operating Temperature Min: 0��C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Operating Temperature Max: 70°C
• Page Size: 128MB
• Memory Case Style: FBGA
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
FUNCTION TRUTH TABLE (TABLE2)
Abbreviations : ABI = All Banks Idle, RA = Row Address
*Note : 6.CKE low to high transition is asynchronous.
Elite Semiconductor Memory Technology Inc.
Precharge
other than
Any State
Current
Refresh
Banks
Power
Banks
above
Listed
Down
State
Self
Idle
All
All
7.CKE low to high transition is asynchronous if restart internal clock.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
A minimum setup time 1CLK + t
( n-1 )
CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CKE
X
H
H
H
H
H
X
H
H
H
H
H
H
H
H
n
L
L
L
L
L
L
L
L
L
L
L
L
L
CS RAS CAS WE
H
H
H
X
X
X
L
L
X
X
L
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
SS
must be satisfy before any command other than exit.
H
H
H
H
H
H
H
H
X
X
X
L
X
X
X
X
L
X
X
X
X
L
L
L
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
X
H
X
H
H
X
X
X
X
X
L
L
L
L
L
OP Code
ADDR
RA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh
Exit Self Refresh
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh
Exit Self Refresh
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
NOP
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
ACTION
Publication Date: Oct. 2007
Revision: 1.1
Idle after tRFC (ABI)
Idle after tRFC (ABI)
ABI
ABI
M52S128168A
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Note
6
6
7
7
8
8
8
9
9