M52S128168A-7.5BG ELITE SEMICONDUCTOR, M52S128168A-7.5BG Datasheet - Page 6

• Manufacturer Part Number: M52S128168A-7.5BG
• Description: DRAM IC
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5BG

• Ic Interface Type: Parallel
• Frequency: 133MHz
• Termination Type: SMD
• Supply Voltage Max: 2.7V
• Memory Voltage, Vcc: 2.5 V
• Interface Type: Parallel
• Memory Size: 128Mbit
• Supply Voltage Min: 2.3V
• Operating Temperature Min: 0��C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Operating Temperature Max: 70°C
• Page Size: 128MB
• Memory Case Style: FBGA
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC OPERATING TEST CONDITIONS (V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
Elite Semiconductor Memory Technology Inc.
RAS to CAS delay
Row active time
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or Refresh Command
Number of valid output data
Refresh period(4,096 rows)
5. A new command may be given T
6. A maximum of eight consecutive AUTO REFRESH commands (with t
3. Minimum delay is required to complete write.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
then rounding off to the next higher integer.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Parameter
@Operating
@Auto refresh
Parameter
DD
rfc
after self refresh exit.
=2.5V
±
0.2V,T
Symbol
CAS latency=3
CAS latency=2
A
= 0 C
t
t
t
t
t
t
t
t
t
t
t
t
t
RRD
RCD
RP
RAS
RAS
RC
RFC
CDL
RDL
BDL
CCD
MRD
REF
°
(min)
(min)
(min)
(min)
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(max)
~ 70 C
0.9 x V
tr / tf = 1 / 1
0.5 x V
0.5 x V
See Fig.2
° )
Value
DDQ
DDQ
DDQ
RFCmin
/ 0.2
14
14
14
42
63
-7
) can be posted to any given SDRAM,and
Version
67.5
-7.5
100
15
15
15
48
80
64
1
2
1
1
2
2
1
Publication Date: Oct. 2007
Revision: 1.1
-10
20
20
20
50
90
M52S128168A
Unit
CLK
CLK
CLK
CLK
CLK
ms
ns
ns
ns
ns
ns
ea
us
ns
Unit
ns
V
V
V
6/47
Note
1 , 5
1
1
1
1
1
2
2
2
3
4
6
-
-