M52S128168A-7.5BG ELITE SEMICONDUCTOR, M52S128168A-7.5BG Datasheet - Page 31

• Manufacturer Part Number: M52S128168A-7.5BG
• Description: DRAM IC
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5BG

• Ic Interface Type: Parallel
• Frequency: 133MHz
• Termination Type: SMD
• Supply Voltage Max: 2.7V
• Memory Voltage, Vcc: 2.5 V
• Interface Type: Parallel
• Memory Size: 128Mbit
• Supply Voltage Min: 2.3V
• Operating Temperature Min: 0��C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Operating Temperature Max: 70°C
• Page Size: 128MB
• Memory Case Style: FBGA
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
Note :
Elite Semiconductor Memory Technology Inc.
1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
BA1
A10/AP
A10/AP
0
0
1
1
0
1
0
0
0
0
1
BA0
0
1
0
1
BA1
BA1
X
0
0
1
1
0
0
1
1
0
0
1
1
Active & Read/Write
BA0
BA0
X
0
1
0
1
0
1
0
1
0
1
0
1
Bank C
Bank D
Bank A
Bank B
Disable auto precharge, leave A bank active at end of burst.
Disable auto precharge, leave B bank active at end of burst.
Disable auto precharge, leave C bank active at end of burst.
Disable auto precharge, leave D bank active at end of burst.
Enable auto precharge , precharge bank A at end of burst.
Enable auto precharge , precharge bank B at end of burst.
Enable auto precharge , precharge bank C at end of burst.
Enable auto precharge , precharge bank D at end of burst.
Precharge
All Banks
Bank C
Bank D
Bank A
Bank B
Operating
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
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