M52S128168A-7.5BG ELITE SEMICONDUCTOR, M52S128168A-7.5BG Datasheet - Page 3

• Manufacturer Part Number: M52S128168A-7.5BG
• Description: DRAM IC
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5BG

• Ic Interface Type: Parallel
• Frequency: 133MHz
• Termination Type: SMD
• Supply Voltage Max: 2.7V
• Memory Voltage, Vcc: 2.5 V
• Interface Type: Parallel
• Memory Size: 128Mbit
• Supply Voltage Min: 2.3V
• Operating Temperature Min: 0��C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Operating Temperature Max: 70°C
• Page Size: 128MB
• Memory Case Style: FBGA
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
Elite Semiconductor Memory Technology Inc.
CLK
CKE
A0 ~ A11
BA0 , BA1
L(U)DQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
RAS
CS
CAS
WE
Address
PIN
CLK
CKE
CS
RAS
CAS
WE
Clock
Generator
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
NAME
Mode
Register
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
RAS low.
CAS low.
Row
Address
Buffer
Refresh
Counter
Column
Address
Buffer
Refresh
Counter
&
&
Data Control Circuit
INPUT FUNCTION
Column Decoder
SHZ
Sense Amplifier
after the clock and masks the output.
Bank A
Bank B
Bank C
Bank D
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
L(U)DQM
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DQ