M52S128168A-7.5BG ELITE SEMICONDUCTOR, M52S128168A-7.5BG Datasheet - Page 26

• Manufacturer Part Number: M52S128168A-7.5BG
• Description: DRAM IC
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5BG

• Ic Interface Type: Parallel
• Frequency: 133MHz
• Termination Type: SMD
• Supply Voltage Max: 2.7V
• Memory Voltage, Vcc: 2.5 V
• Interface Type: Parallel
• Memory Size: 128Mbit
• Supply Voltage Min: 2.3V
• Operating Temperature Min: 0��C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Operating Temperature Max: 70°C
• Page Size: 128MB
• Memory Case Style: FBGA
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
12. About Burst Type Control
13. About Burst Length Control
Elite Semiconductor Memory Technology Inc.
Random
Random
Interrupt
MODE
MODE
MODE
MODE
MODE
Basic
Basic
Random Column Access
(Interrupted by
RAS Interrupt
CAS Interrupt
Sequential Counting
Precharge)
Interleave Counting
Burst Stop
Full Page
t
CCD
1
2
4
8
= 1 CLK
burst.
At MRS A210 = “000”
At auto precharge . t
At MRS A210 = “001”
At auto precharge . t
At MRS A210 = “010”
At MRS A210 = “011”
At MRS A210 = “111”
At the end of the burst length , burst is warp-around.
t
Using burst stop command, any burst length control is possible.
Before the end of burst. Row precharge command of the same bank stops read /write burst
t
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new read/write
During read/write burst with auto precharge, CAS interrupt can not be issued.
with auto precharge.
BDL
RDL
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
= 2clk with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
RAS
RAS
should not be violated.
should not be violated.
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
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