CS1W-CN313 Omron, CS1W-CN313 Datasheet - Page 67

• Manufacturer Part Number: CS1W-CN313
• Description: "CABLE CS1 EXP I/O,30cm"
• Manufacturer: Omron

Specifications of CS1W-CN313

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Unit Specifications
2-1-2
Performance Specifications
Control method
I/O control method
Programming language
I/O capacity
Program capacity
Data memory capacity
Instruction length
Number of instructions in instruction
set
Instruction execution times
Overseeing time
Mounting structure
Mounting
CPU Unit built-in DC input points
Maximum number of Units
Inner Boards
Communications Units
Types of
interrupts
I/O allocation
CPU Unit Specifications
Item
Input interrupts
(4 points max.)
Interval timer
interrupts
(3 points max.)
High-speed
counter interrupt
CQM1H-CPU11/21:
CQM1H-CPU51/61:
CQM1H-CPU11/21:
CQM1H-CPU51:
CQM1H-CPU61:
CQM1H-CPU11/21:
CQM1H-CPU51:
CQM1H-CPU61:
1 to 4 words per instruction
162 (14 basic, 148 special instructions)
Basic instructions:
Special instructions:
0.70 ms
No Backplane (Units are joined horizontally using connectors)
must also be counted.)
CPU Block only:
CPU Block and Expansion I/O Block
CPU Block:
Expansion I/O Block:
CQM1H-CPU11/21:
CQM1H-CPU51/61:
CQM1H-CPU11/21:
CQM1H-CPU51/61:
Input Interrupt Mode: Interrupt is executed in response to input from an external
source to the CPU Unit’s built-in input points.
Counter Mode: Interrupt is executed in response to input received a certain
number of times (counted down) via the CPU Unit’s internal built-in input points
(4 points).
Scheduled Interrupt Mode: Program is interrupted at regular intervals measured by
one the CPU Unit’s internal timers.
One-shot Interrupt Mode: One interrupt is executed after a certain time, measured
by one of the CPU Unit’s internal timers.
Target Value Comparison: Interrupt is executed when the high-speed counter PV
is equal to a specified value.
Range Comparison: Interrupt is executed when the high-speed counter PV lies
within a specified range.
Note Counting is possible for high-speed counter inputs from the CPU Unit’s inter-
I/O is automatically allocated in order from the Unit nearest to the CPU Unit.
(Because there are no I/O tables, it is not necessary, and not possible, to create
I/O tables from a Programming Device.)
Stored program method
Cyclic scan and direct output/immediate interrupt processing used together
Ladder diagram
DIN Track mounting (screw mounting not possible)
16
Maximum number of I/O and Dedication I/O Units (Analog Power Supply Units
nal input points, Pulse I/O Boards, or Absolute Encoder
Interface Boards. (The High-speed Counter Board has no interrupt function,
and can only output bit patterns internally and externally.)
256
512
3.2 Kwords
7.2 Kwords
15.2 Kwords
3 Kwords
6 Kwords
12 Kwords (DM: 6 Kwords; EM: 6 Kwords)
None
2 Boards
None
1 Unit
0.375 to 1.125 s
17.7 s (MOV instruction)
11 Units max.
5 Units max.
11 Units max.
Specifications
Section 2-1
45