XC3S1000-4FG456I Xilinx Inc, XC3S1000-4FG456I Datasheet - Page 120

• Manufacturer Part Number: XC3S1000-4FG456I
• Description: FIELD PROGRAMMABLE GATE ARRAY
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1000-4FG456I

• Number Of Logic Elements/cells: 17280
• Number Of Labs/clbs: 1920
• Total Ram Bits: 442368
• Number Of I /o: 333
• Number Of Gates: 1000000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 333
• Ram Bits: 442368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan-3 FPGA Family: Pinout Descriptions
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table
Table 82: Xilinx Package Mechanical Drawings
Power, Ground, and I/O by Package
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions varies by package, as shown in
Table 83: Power and Ground Supply Pins by Package
120
Notes:
1.
Notes:
1.
FG1156
Package
CP132
VQ100
PQ208
TQ144
FG320
FG456
FG676
FG900
FT256
The CP132, CPG132, FG1156, and FGG1156 packages are being discontinued and are not recommended for new designs. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm
The CP132, CPG132, FG1156, and FGG1156 packages are
being discontinued and are not recommended for new
designs. See
http://www.xilinx.com/support/documentation/
spartan-3_customer_notices.htm
82.
FG1156 and FGG1156
(1)
(1)
CP132 and CPG132
VQ100 and VQG100
PQ208 and PQG208
TQ144 and TQG144
FG320 and FGG320
FG456 and FGG456
FG676 and FGG676
FG900 and FGG900
FT256 and FTG256
VCCINT
Package
12
12
20
32
40
4
4
4
4
8
VCCAUX
(1)
16
24
32
(1)
4
4
4
8
8
8
8
for the latest updates.
VCCO
104
12
12
12
24
28
40
64
80
8
http://www.xilinx.com/support/documentation/package_specs/fg1156.pdf
http://www.xilinx.com/support/documentation/package_specs/pq208.pdf
http://www.xilinx.com/support/documentation/package_specs/vq100.pdf
http://www.xilinx.com/support/documentation/package_specs/cp132.pdf
http://www.xilinx.com/support/documentation/package_specs/tq144.pdf
http://www.xilinx.com/support/documentation/package_specs/fg320.pdf
http://www.xilinx.com/support/documentation/package_specs/fg456.pdf
http://www.xilinx.com/support/documentation/package_specs/fg676.pdf
http://www.xilinx.com/support/documentation/package_specs/fg900.pdf
Table
http://www.xilinx.com/support/documentation/package_specs/ft256.pdf
GND
120
184
10
12
16
28
32
40
52
76
www.xilinx.com
83.
Material Declaration Data Sheets (MDDS) are also avail-
able on the
A majority of package pins are user-defined I/O pins. How-
ever, the numbers and characteristics of these I/O depends
on the device type and the package in which it is available,
as shown in
ber of single-ended I/O pins available, assuming that all
I/O-, DUAL-, DCI-, VREF-, and GCLK-type pins are used as
general-purpose I/O. Likewise, the table shows the maxi-
mum number of differential pin-pairs available on the pack-
age. Finally, the table shows how the total maximum user
I/Os are distributed by pin type, including the number of
unconnected—i.e., N.C.—pins on the device.
Web Link (URL)
Xilinx website
Table
for the latest updates.
84. The table shows the maximum num-
for each package.
DS099-4 (v2.5) December 4, 2009
Product Specification
R