XC3S1000-4FG456I Xilinx Inc, XC3S1000-4FG456I Datasheet - Page 63

• Manufacturer Part Number: XC3S1000-4FG456I
• Description: FIELD PROGRAMMABLE GATE ARRAY
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1000-4FG456I

• Number Of Logic Elements/cells: 17280
• Number Of Labs/clbs: 1920
• Total Ram Bits: 442368
• Number Of I /o: 333
• Number Of Gates: 1000000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 333
• Ram Bits: 442368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 35: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
3.
4.
5.
6.
7.
LVCMOS33
LVDCI_33,
LVDCI_DV2_33
LVTTL
PCI33_3
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
(IOSTANDARD) and Current
The numbers in this table are based on the conditions set forth in
Descriptions of the symbols used in this table are as follows:
Tested according to the standard’s relevant specifications. When using the DCI version of a standard on a given I/O bank, that bank
will consume more power than if the non-DCI version had been used instead. The additional power is drawn for the purpose of
impedance-matching at the I/O pins. A portion of this power is dissipated in the two R
For the LVCMOS and LVTTL standards: the same V
All dedicated output pins (CCLK, DONE, and TDO) and dual-purpose totem-pole output pins (D0-D7 and BUSY/DOUT) exhibit the
characteristics of LVCMOS25 with 12 mA drive and slow slew rate. For information concerning the use of 3.3V signals, see the
3.3V-Tolerant Configuration Interface, page
Tested according to the relevant PCI specifications. For more information, see XAPP457.
The minimum usable V
I
I
V
V
V
V
V
V
V
OL
OH
Drive Attribute (mA)
OL
OH
IL
IH
CCO
REF
TT
(4)
Signal Standard
–
–
–
–
–
–
–
(7)
–
the input voltage that indicates a Low logic level
the output current condition under which V
the output current condition under which V
the input voltage that indicates a High logic level
–
the voltage applied to a resistor termination
the output voltage that indicates a Low logic level
the output voltage that indicates a High logic level
(4)
R
the reference voltage for setting the input switching threshold
the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
(7)
12
16
24
12
16
24
2
4
6
8
2
4
6
8
TT
voltage is 1.25V
Note 3
Note 6
Note 3
Note 3
Note 3
(mA)
13.4
16.2
I
6.7
8.1
12
16
24
12
16
24
OL
2
4
6
8
2
4
6
8
Spartan-3 FPGA Family: DC and Switching Characteristics
46.
Test Conditions
OL
OH
OL
is tested
is tested
www.xilinx.com
and V
OH
limits apply for both the Fast and Slow slew attributes.
Note 3
Note 6
Note 3
Note 3
Note 3
–13.4
–16.2
(mA)
Table 31
–6.7
–8.1
–12
–16
–24
–12
–16
–24
I
–2
–4
–6
–8
–2
–4
–6
–8
OH
and
Table
34.
REF
V
V
0.10V
V
V
TT
TT
Max (V)
resistors.
TT
TT
Logic Level Characteristics
V
0.4
0.4
- 0.475
- 0.475
- 0.61
- 0.81
OL
CCO
V
V
V
V
V
0.90V
TT
TT
CCO
TT
TT
Min (V)
V
2.4
+ 0.475
+ 0.475
+ 0.61
+ 0.81
OH
- 0.4
CCO
63