XC3S1000-4FG456I Xilinx Inc, XC3S1000-4FG456I Datasheet - Page 196

• Manufacturer Part Number: XC3S1000-4FG456I
• Description: FIELD PROGRAMMABLE GATE ARRAY
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1000-4FG456I

• Number Of Logic Elements/cells: 17280
• Number Of Labs/clbs: 1920
• Total Ram Bits: 442368
• Number Of I /o: 333
• Number Of Gates: 1000000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 333
• Ram Bits: 442368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan-3 FPGA Family: Pinout Descriptions
FG1156: 1156-lead Fine-pitch Ball Grid
Array
The 1,156-lead fine-pitch ball grid array package, FG1156,
supports two different Spartan-3 devices, namely the
XC3S4000 and the XC3S5000. The XC3S4000, however,
has fewer I/O pins, which consequently results in 73 uncon-
nected pins on the FG1156 package, labeled as “N.C.” In
Table 109
cated with a black diamond symbol ( ).
The XC3S5000 has a single unconnected package pin, ball
AK31, which is also unconnected for the XC3S4000.
All the package pins appear in
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S4000 and
XC3S5000 pinouts, then that difference is highlighted in
Table
unconnected pin on the XC3S4000 that maps to a user-I/O
pin on the XC3S5000. If the table entry is shaded tan, which
only occurs on ball L29 in I/O Bank 2, then the unconnected
pin on the XC3S4000 maps to a VREF-type pin on the
XC3S5000. If the other VREF_2 pins all connect to a volt-
age reference to support a special I/O standard, then also
connect the N.C. pin on the XC3S4000 to the same
VREF_2 voltage.
Pinout Table
Table 109: FG1156 Package Pinout
196
Bank
Note: The FG(G)1156 package is being discontinued and is
not recommended for new designs. See
http://www.xilinx.com/support/documentation/
spartan-3_customer_notices.htm
0
0
0
0
0
0
0
0
0
0
0
0
0
109. If the table entry is shaded grey, then there is an
and
IO
IO
IO
IO
IO
IO
IO
IO
N.C. ( )
N.C. ( )
IO
IO
IO
XC3S4000
Pin Name
Figure
51, these unconnected pins are indi-
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
XC3S5000
Pin Name
Table 109
for the latest updates.
Number
FG1156
and are sorted by
G12
E17
K11
K13
K16
K17
Pin
J11
H8
H9
B9
F6
F8
J9
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 109: FG1156 Package Pinout (Continued)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/
VRP_0
IO_L01P_0/
VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0/
VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
XC3S4000
Pin Name
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/
VRP_0
IO_L01P_0/
VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0/
VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
XC3S5000
Pin Name
DS099-4 (v2.5) December 4, 2009
Product Specification
Number
FG1156
H10
G10
H12
D12
C12
H13
G13
E10
F10
K12
F12
E12
B12
A12
Pin
L13
L16
L17
J14
L15
J10
L12
J12
D5
C5
D6
C6
G9
D9
C9
B3
A3
B4
A4
B5
B6
A6
F7
E7
F9
VREF
VREF
VREF
VREF
VREF
Type
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R