XC3S1000-4FG456I Xilinx Inc, XC3S1000-4FG456I Datasheet - Page 40

• Manufacturer Part Number: XC3S1000-4FG456I
• Description: FIELD PROGRAMMABLE GATE ARRAY
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1000-4FG456I

• Number Of Logic Elements/cells: 17280
• Number Of Labs/clbs: 1920
• Total Ram Bits: 442368
• Number Of I /o: 333
• Number Of Gates: 1000000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 333
• Ram Bits: 442368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan-3 FPGA Family: Functional Description
Table 20: Signals for Variable Phase Mode
The Variable Phase Mode
The “Variable Phase” mode dynamically adjusts the fine
phase shift over time using three inputs to the PS compo-
nent, namely PSEN, PSCLK and PSINCDEC, as defined in
Table
After device configuration, the PS component initially deter-
mines T
to the PHASE_SHIFT attribute. Then to dynamically adjust
that phase shift, use the three PS inputs to increase or
decrease the fine phase shift.
PSINCDEC is synchronized to the PSCLK clock signal,
which is enabled by asserting PSEN. It is possible to drive
the PSCLK input with the CLKIN signal or any other clock
signal. A request for phase adjustment is entered as follows:
For each PSCLK cycle that PSINCDEC is High, the PS
component adds 1/256 of a CLKIN cycle to T
for each enabled PSCLK cycle that PSINCDEC is Low, the
PS component subtracts 1/256 of a CLKIN cycle from T
The phase adjustment may require as many as 100 CLKIN
cycles plus three PSCLK cycles to take effect, at which
Table 21: Status Logic Signals
40
54
Notes:
1.
PSEN
PSCLK
PSINCDEC
PSDONE
RST
STATUS[7:0]
LOCKED
It is possible to program this input for either a true or inverted polarity
Signal
Signal
20.
(1)
PS
(1)
by evaluating Equation (4) for the value assigned
(1)
Direction
Direction
Output
Output
Output
Input
Input
Input
Input
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay
of zero. Sets the LOCKED output Low. This input is asynchronous.
The bit values on the STATUS bus provide information regarding the state of DLL and PS
operation
are out-of-phase when Low.
Enables PSCLK for variable phase adjustment.
Clock to synchronize phase shift adjustment.
Chooses between increment and decrement for phase adjustment. It is synchronized to the
PSCLK signal.
Goes High to indicate that present phase adjustment is complete and PS component is
ready for next phase adjustment request. It is synchronized to the PSCLK signal.
PS
. Similarly,
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PS
.
point the output PSDONE goes High for one PSCLK cycle.
This pulse indicates that the PS component has finished the
present adjustment and is now ready for the next request.
Asserting the Reset (RST) input, returns T
shift time, as determined by the PHASE_SHIFT attribute
value. The set of waveforms in
relationship between CLKFB and CLKIN in the Variable
Phase mode.
The Status Logic Component
The Status Logic component not only reports on the state of
the DCM but also provides a means of resetting the DCM to
an initial known state. The signals associated with the Sta-
tus Logic component are described in
As a rule, the Reset (RST) input is asserted only upon con-
figuring the device or changing the CLKIN frequency. A
DCM reset does not affect attribute values (e.g.,
CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST
must be tied to GND.
The eight bits of the STATUS bus are defined in
Description
Description
DS099-2 (v2.5) December 4, 2009
Figure 21c
Table
Product Specification
PS
21.
illustrates the
to its original
Table
22.
R