XC3S1000-4FG456I Xilinx Inc, XC3S1000-4FG456I Datasheet - Page 216

• Manufacturer Part Number: XC3S1000-4FG456I
• Description: FIELD PROGRAMMABLE GATE ARRAY
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1000-4FG456I

• Number Of Logic Elements/cells: 17280
• Number Of Labs/clbs: 1920
• Total Ram Bits: 442368
• Number Of I /o: 333
• Number Of Gates: 1000000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 333
• Ram Bits: 442368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan-3 FPGA Family: Pinout Descriptions
Revision History
216
04/03/03
04/21/03
05/12/03
07/11/03
07/29/03
08/19/03
10/09/03
12/17/03
02/27/04
07/13/04
08/24/04
01/17/05
08/19/05
04/03/06
04/26/06
Date
Version No.
1.1.1
1.1.2
1.2.1
1.2.2
1.5.1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.0
2.1
Initial Xilinx release.
Added information on the VQ100 package footprint, including a complete pinout table
footprint diagram
final differential I/O pair counts for the TQ144 package. Added clarifying comments to HSWAP_EN pin
description on
Figure
Figure
column in
AM32 pin was missing GND label in FG1156 package diagram
Corrected misspellings of GCLK in
Dual-Purpose Pin I/O Standard During Configuration
XC3S5000 in FG1156 package, corrected N.C. symbol to a black square in
drawing.
Corrected pin names on FG1156 package. Some package balls incorrectly included LVDS pair names.
The affected balls on the FG1156 package include G1, G2, G33, G34, U9, U10, U25, U26, V9, V10, V25,
V26, AH1, AH2, AH33, AH34. The number of LVDS pairs is unaffected. Modified affected balls and
re-sorted rows in
electronic versions of FG1156 pinout.
Removed 100 MHz ConfigRate option in
note that TDO is a totem-pole output in
Some pins had incorrect bank designations and were improperly sorted in
functions changed. Renamed DCI_IN to DCI and added black diamond to N.C. pins in
Figure
Added FG320 pin tables and pinout diagram
cosmetic changes to the TQ144 footprint
footprint
the JTAG Port in 3.3V Environments
Clarified wording in
for FG320 and increased maximum I/O values for the FG676, FG900, and FG1156 packages.
Added information on lead-free (Pb-free) package options to the
Table 80
single termination as described in the
from Advance Product Specification to Product Specification.
Removed XC3S2000 references from
Added XC3S50 in CP132 package option. Added XC3S2000 in FG456 package option. Added
XC3S4000 in FG676 package option. Added
added
Table
Removed term “weak” from the description of pull-up and pull-down resistors. Added
values. Added signal integrity precautions to
should be treated as an I/O during Master mode in
Added
Added detail about which pins have dedicated pull-up resistors during configuration, regardless of the
HSWAP_EN value to
When Using the JTAG Port in 3.3V
Corrected swapped data row in
Theta-JC column. Made additional notations on CONFIG and JTAG pins that have pull-up resistors
during configuration, regardless of the HSWAP_EN input.
105,
50b. Some thick lines separating I/O banks were incorrect. Made cosmetic changes to
40, and
45, removed some extraneous text from pin 106 and corrected spelling of pins 45, 48, and 81.
Table
Package Thermal
(Figure
and
Table
Figure
80,
Table
page
Figure
90.
49), and the FG900 footprint
Table
(Figure
Table
43, and
Using JTAG Port After Configuration
82. Clarified the VRN_# reference resistor requirements for I/O standards that use
111. Updated the footprint diagram for the FG900 package shown in
Table 69
41. Updated Xilinx hypertext links. Added XC3S200 and XC3S400 to Pin Name
82,
109. Updated affected balls in
42). Updated
Figure
Characteristics. Updated
Table
www.xilinx.com
and to
Table
83,
49.
Table 68
Table
Environments.
Pin Behavior During
85. The Theta-JA with zero airflow column was swapped with the
DCI Termination Types
FG1156: 1156-lead Fine-pitch Ball Grid
Table 84
section.
Table
CCLK: Configuration Clock
(Figure
84,
and
(Figure
Selecting the Right Package Option
CCLK: Configuration Clock
(FG320: 320-lead Fine-pitch Ball Grid
Description
76.
Table
with final I/O counts for the VQ100 package. Also added
Table
44), the PQ208 footprint
Table
88,
50). Clarified wording in
Figure 39
Figure
69. Changed CMOS25 to LVCMOS25 in
Table
section. Clarified references to Module 2. For
78.
section. In
Configuration. Updated
51. Also updated ASCII and Excel
89,
section and in
(Figure
to make it a more obvious example.
Package Overview
Table
Table
DS099-4 (v2.5) December 4, 2009
51).
section and in
99,
(Figure
Table
Table
and indicated that CCLK
80, reduced package height
Table
Precautions When Using
Figure
Array.
92. No pin names or
109, key, and package
Product Specification
101,
45), the FG676
section. Modified or
IDCODE Register
40b. Graduated
section plus
Array). Made
Precautions
Table
(Table
Table
Table
Figure 50a
79. Added
102,
86) and
92. In
Figure
and
38,
R