XC3S1000-4FG456I Xilinx Inc, XC3S1000-4FG456I Datasheet - Page 21

• Manufacturer Part Number: XC3S1000-4FG456I
• Description: FIELD PROGRAMMABLE GATE ARRAY
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1000-4FG456I

• Number Of Logic Elements/cells: 17280
• Number Of Labs/clbs: 1920
• Total Ram Bits: 442368
• Number Of I /o: 333
• Number Of Gates: 1000000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 333
• Ram Bits: 442368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2. Set all V
3. The V
4. Only one of the following standards is allowed on
5. If none of the standards assigned to the I/Os of the
6. In general, apply 2.5V to V
If any of the standards assigned to the Inputs of the bank
use V
1. Connect all V
2. The V
If none of the standards assigned to the Inputs of a bank
use V
ated V
Exceptions to Banks Supporting I/O
Standards
Bank 5 of any Spartan-3 device in a VQ100, CP132, or
TQ144 package does not support DCI signal standards. In
this case, bank 5 has neither VRN nor VRP pins.
Furthermore, banks 4 and 5 of any Spartan-3 device in a
VQ100 package do not support signal standards using
V
any V
Supply Voltages for the IOBs
Three different supplies power the IOBs:
1. The V
DS099-2 (v2.5) December 4, 2009
Product Specification
REF
bank to the same voltage level.
I/Os of the (interconnected) bank(s) must agree. The
Xilinx development software checks for this. Tables 7, 8,
and
supply.
outputs per bank: LVDS, LDT, LVDS_EXT, or RSDS.
This restriction is for the eight banks in each device,
even if the V
the CP132 and TQ144 packages.
(interconnected) bank(s) uses V
V
the end of configuration. Apply the same voltage to
V
Readback operation. For information on how to
program the FPGA using 3.3V signals and power, see
the
voltage level.
Inputs of the bank must agree. The Xilinx development
software checks for this. Tables
different standards use the V
banks, power the output drivers, except when using the
GTL and GTLP signal standards. The voltage on the
V
signal.
CCO
CCO
(see
CCO
REF
REF
REF
REF
3.3V-Tolerant Configuration Interface
9
, then observe the following additional rules:
pins.
CCO
REF
CCO
lines to 2.5V.
Bank 5 during parallel configuration or a
for biasing input switching thresholds, all associ-
pins determines the voltage swing of the output
describe how different standards use the V
Table
pins function as User I/Os.
R
CCO
levels used by all standards assigned to the
levels used by all standards assigned to the
supplies, one for each of the FPGA’s I/O
CCO
7). In this case, the two banks do not have
lines associated with the (interconnected)
REF
levels are shared across banks, as in
pins within the bank to the same
CCO
REF
Bank 4 from power-on to
7
CCO
supply.
and
, tie all associated
9
describe how
section.
CCO
www.xilinx.com
2. V
3. The V
The I/Os During Power-On, Configuration, and
User Mode
With no power applied to the FPGA, all I/Os are in a
high-impedance state. The V
and V
power-on can finish, V
must have reached their respective minimum recom-
mended operating levels (see
time, all I/O drivers also will be in a high-impedance state.
V
internal Power-On Reset circuit (POR).
A Low level applied to the HSWAP_EN input enables
pull-up resistors on User I/Os from power-on throughout
configuration. A High level on HSWAP_EN disables the
pull-up resistors, allowing the I/Os to float. If the
HSWAP_EN pin is floating, then an internal pull-up resistor
pulls HSWAP_EN High. As soon as power is applied, the
FPGA begins initializing its configuration memory. At the
same time, the FPGA internally asserts the Global
Set-Reset (GSR), which asynchronously resets all IOB stor-
age elements to a Low state.
Upon the completion of initialization, INIT_B goes High,
sampling the M0, M1, and M2 inputs to determine the con-
figuration mode. At this point, the configuration data is
loaded into the FPGA. The I/O drivers remain in a
high-impedance state (with or without pull-up resistors, as
determined by the HSWAP_EN input) throughout configura-
tion.
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the begin-
ning of design operation in the User mode. At this point,
those I/Os to which signals have been assigned go active
while all unused I/Os remain in a high-impedance state. The
release of the GSR net, also part of Start-up, leaves the IOB
registers in a Low state by default, unless the loaded design
reverses the polarity of their respective RS inputs.
In User mode, all internal pull-up resistors on the I/Os are
disabled and HSWAP_EN becomes a “don’t care” input. If it
is desirable to have pull-up or pull-down resistors on I/Os
carrying signals, the appropriate symbol — e.g., PULLUP,
PULLDOWN — must be placed at the appropriate pads in
the design. The Bitstream Generator (Bitgen) option
UnusedPin available in the Xilinx development software
determines whether unused I/Os collectively have pull-up
resistors, pull-down resistors, or no resistors in User mode.
CCO
logic.
optimize the performance of various FPGA functions
such as I/O switching.
CCINT
CCO
Bank 4, V
Spartan-3 FPGA Family: Functional Description
CCAUX
is the main power supply for the FPGA’s internal
supplies may be applied in any order. Before
is an auxiliary source of power, primarily to
CCINT
, and V
CCINT
, V
CCINT
CCAUX
Table 28, page
CCO
(1.2V), V
serve as inputs to the
Bank 4, and V
CCAUX
56). At this
(2.5V),
CCAUX
21