XC3S1000-4FG456I Xilinx Inc, XC3S1000-4FG456I Datasheet - Page 48

• Manufacturer Part Number: XC3S1000-4FG456I
• Description: FIELD PROGRAMMABLE GATE ARRAY
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S1000-4FG456I

• Number Of Logic Elements/cells: 17280
• Number Of Labs/clbs: 1920
• Total Ram Bits: 442368
• Number Of I /o: 333
• Number Of Gates: 1000000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 456-BBGA
• Package: 456FBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 333
• Ram Bits: 442368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan-3 FPGA Family: Functional Description
when operating in the User mode. This is accomplished by
setting the Persist option to Yes.
Multiple FPGAs can be configured using the Slave Parallel
mode and can be made to start-up simultaneously.
Figure 25
48
54
Notes:
1.
2.
3.
There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA
to be configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE pin to drive
High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain. Second,
DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in
grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE synchronously with a long
chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise
time within one clock cycle.
If the FPGAs use different configuration data files, configure them in sequence by first asserting the CS_B of one FPGA then
asserting the CS_B of the other FPGA.
For information on how to program the FPGA using 3.3V signals and power, see
shows the device connections. To configure mul-
RDWR_B
PROG_B
INIT_B
DONE
BUSY
D[0:7]
CCLK
4.7KΩ
Figure 25: Connection Diagram for Slave Parallel Configuration
2.5V
4.7KΩ
CS_B
2.5V
V
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROG_B
DONE
V
CCAUX
CCO
Spartan-3
Slave
Banks 4 & 5
GND
INIT_B
V
www.xilinx.com
CCINT
M1
M2
M0
1.2V
2.5V
tiple devices in this way, wire the individual CCLK, Data,
RDWR_B, and BUSY pins of all the devices in parallel. The
individual devices are loaded separately by deasserting the
CS_B pin of each device in turn and writing the appropriate
data.
CS_B
2.5V
V
V
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROG_B
DONE
3.3V-Tolerant Configuration
CCAUX
CCO
Spartan-3
Slave
Banks 4 & 5
GND
INIT_B
V
CCINT
M1
M2
M0
DS099-2 (v2.5) December 4, 2009
2.5V
1.2V
DS099_24_041103
Product Specification
Interface.
R