ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 18

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
JTAG Test Access Port (TAP) on each JTAG processor. The
emulator uses the TAP to access the internal features of the pro-
cessor, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
processor must be halted to send data and commands, but once
an operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see (EE-68) Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
ADC AND ACM INTERFACE
This section describes the ADC and ACM interface. System
designers should also consult the ADSP-BF50x Blackfin Proces-
sor Hardware Reference for additional information.
The ADC control module (ACM) provides an interface that
synchronizes the controls between the processor and the inter-
nal analog-to-digital converter (ADC) module. The ACM is
available on the ADSP-BF504, ADSP-BF504F, and
ADSP-BF506F processors, and the ADC is available on the
ADSP-BF506F processor only. The analog-to-digital conver-
sions are initiated by the processor, based on external or
internal events.
The ACM allows for flexible scheduling of sampling instants
and provides precise sampling signals to the ADC.
The ACM synchronizes the ADC conversion process; generat-
ing the ADC controls, the ADC conversion start signal, and
other signals. The actual data acquisition from the ADC is done
by the SPORT peripherals.
The serial interface on the ADC allows the part to be directly
connected to the ADSP-BF504, ADSP-BF504F, and
ADSP-BF506F processors using serial interface protocols.
Rev. 0 | Page 18 of 80 | December 2010
Figure 6
and one of the two SPORTs on the ADSP-BF504 or
ADSP-BF504F processors.
The ADC is integrated into the ADSP-BF506F product.
shows how to connect the internal ADC to the ACM and to one
of the two SPORTs on the ADSP-BF506F processor.
The ADSP-BF504, ADSP-BF504F, and ADSP-BF506F proces-
sors interface directly to the ADC without any glue logic
required. The availability of secondary receive registers on the
serial ports of the Blackfin processors means only one serial port
shows how to connect an external ADC to the ACM
Figure 6. ADC (External), ACM, and SPORT Connections
Figure 7. ADC (Internal), ACM, and SPORT Connections
ADSP-BF504 / ADSP-BF504F
ADSP-BF506F
(EXTERNAL)
(INTERNAL)
SPORTx
SPORTx
ACM
ADC
ACM
ADC
ACM_SGLDIFF
ACM_SGLDIFF
ACM_RANGE
ACM_RANGE
ACM_A[2:0]
ACM_A[2:0]
SGL/
DRxSEC
ADSCLK
DRxSEC
DRxPRI
DRxPRI
RANGE
RCLKx
RCLKx
D
D
ACLK
A[2:0]
RFSx
ACLK
RFSx
OUT
OUT
CS
CS
A
B
SGL/
ADSCLK
RANGE
D
D
A[2:0]
OUT
OUT
SELECT
SELECT
SPORT
SPORT
A
B
MUX
MUX
Figure 7