ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 68

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
down for a relatively long duration between these bursts of sev-
eral conversions. When the ADC is in partial power-down, all
analog circuitry is powered down except for the on-chip refer-
ence and reference buffer.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the sec-
ond falling edge of ADSCLK and before the 10
ADSCLK, as shown in
Mode). Once CS is brought high in this window of ADSCLKs,
the part enters partial power-down, the conversion that was ini-
tiated by the falling edge of CS is terminated, and D
D
second ADSCLK falling edge, the part remains in normal mode
and does not power down. This avoids accidental power-down
due to glitches on the CS line.
To exit this mode of operation and power up the ADC again, a
dummy conversion is performed. On the falling edge of CS, the
device begins to power up and continues to power up as long as
CS is held low until after the falling edge of the 10
The device is fully powered up after approximately 1 μs has
elapsed, and valid data results from the next conversion, as
shown in
is brought high before the second falling edge of ADSCLK, the
ADC again goes into partial power-down. This avoids acciden-
tal power-up due to glitches on the CS line. Although the device
may begin to power up on the falling edge of CS, it powers down
OUT
ADSCLK
D
D
OUT
B go back into three-state. If CS is brought high before the
OUT
CS
A
B
Figure 82 (Exiting Partial Power-Down
Figure 81. Entering Partial Power-Down Mode
ADSCLK
D
D
OUT
OUT
CS
1
A
B
2
Figure 81 (Entering Partial Power-Down
THE PART BEGINS
TO POWER UP.
1
10
INVALID DATA
THREE-STATE
th
falling edge of
th
Mode). If CS
Figure 82. Exiting Partial Power-Down Mode
Rev. 0 | Page 68 of 80 | December 2010
t
POWER-UP1
ADSCLK.
OUT
14
A and
10
14
again on the rising edge of CS. If the ADC is already in partial
power-down mode and CS is brought high between the second
and 10
down mode.
Full Power-Down Mode
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan-
tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions per-
formed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the ADC
is in full power-down, all analog circuitry is powered down. Full
power-down is entered in a similar way as partial power-down,
except the timing sequence shown in
Power-Down
process must be interrupted in a similar fashion by bringing CS
high anywhere after the second falling edge of ADSCLK and
before the 10
tial power-down at this point. To reach full power-down, the
next conversion cycle must be interrupted in the same way, as
shown in
CS is brought high in this window of ADSCLKs, the part com-
pletely powers down.
Note that it is not necessary to complete the 14 ADSCLKs once
CS is brought high to enter a power-down mode.
To exit full power-down and power up the ADC, a dummy con-
version is performed, as when powering up from partial power-
down. On the falling edge of CS, the device begins to power up
and continues to power up, as long as CS is held low until after
the falling edge of the 10
time must elapse before a conversion can be initiated, as shown
in
Up Times
ADC.
Figure 84 (Exiting Full Power-Down
th
falling edges of ADSCLK, the device enters full power-
Figure 83 (Entering Full Power-Down
section for the power-up times associated with the
th
Mode) must be executed twice. The conversion
falling edge of ADSCLK. The device enters par-
1
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
VALID DATA
th
ADSCLK. The required power-up
14
Figure 81 (Entering Partial
Mode). See the
Mode). Once
Power-