ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 38

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Serial Ports
Table 30
through
Table 30. Serial Ports—External Clock
1
2
3
Table 31. Serial Ports—Internal Clock
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
When SPORT is used in conjunction with the ACM, refer to the timing requirements in
Referenced to drive edge.
Referenced to sample edge.
When SPORT is used in conjunction with the ACM, refer to the timing requirements in
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
SCLKIW
DFSI
HOFSI
DDTI
HDTI
Figure 22 on Page 40
through
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
Table 33 on Page 40
describe serial port operations.
and
Figure 20 on Page 39
1,2
1,2
3
3
3
3
3
3
3
3
1,2
1,2
Rev. 0 | Page 38 of 80 | December 2010
1
1
1
1
Table 41 (ACM
Table 41 (ACM
Min
3.0
3.0
3.0
3.5
4.5
2 × t
0.0
0.0
Min
11.0
–1.5
11.5
–1.5
7.0
–2.0
–1.8
SCLK
V
V
DDEXT
DDEXT
Timing).
Timing).
= 1.8 V
= 1.8 V
Max
10.0
11.0
Max
4.0
4.0
Min
3.0
3.0
3.0
3.0
4.5
2 × t
0.0
0.0
Min
9.6
–1.5
10.0
–1.5
8.0
–1.0
–1.5
V
SCLK
V
DDEXT
DDEXT
= 2.5 V/3.3 V
= 2.5 V/3.3 V
Max
10.0
10.0
Max
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns