ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 57

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC—TIMING SPECIFICATIONS
Table 50. Serial Data Interface
1
2
3
ADC—ABSOLUTE MAXIMUM RATINGS
Stresses above those listed in
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 51. Absolute Maximum Ratings
1
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
See
Parameter
AV
DV
V
V
AV
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
V
Input Current to Any ADC Pin
Except Supplies
Storage Temperature Range
Junction Temperature Under Bias
Minimum ADSCLK for specified performance; with slower ADSCLK frequencies, performance specifications apply typically.
The time required for the output to cross 0.4 V or 2.4 V.
Transient currents of up to 100 mA will not cause latch up.
ADSCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
DRIVE
DRIVE
REF
3
DD
DD
DD
Figure 87 on Page 71
to AGND
, DV
to DV
to DGND
to DGND
to AGND
2
DD
DD
to AGND
1
Specification
1/32
14 × t
437.5
560.0
583.3
30
18/23
15
27/36
0.45 t
0.45 t
5/10
15
30
5/35
and
ADSCLK
ADSCLK
ADSCLK
Figure 88 on Page
Table 51
1
may cause permanent
71.
Rating
–0.3 V to +7 V
–0.3 V to +7 V
–0.3 V to DV
–0.3 V to AV
–0.3 V to +0.3 V
–0.3 V to +0.3 V
–0.3 V to AV
–0.3 V to +7 V
–0.3 V to V
–0.3 V to AV
±10 mA
See
See
Unit
MHz min/max
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min/max
Table 20 on Page 30
Table 20 on Page 30
Rev. 0 | Page 57 of 80 | December 2010
DRIVE
DD
DD
DD
DD
+ 0.3 V
+ 0.3 V
+ 0.3 V
Test Conditions / Comments
t
f
f
f
Minimum time between end of serial read and next falling edge of CS
CS to ADSCLK setup time; V
Delay from CS until D
Data access time after ADSCLK falling edge, V
ADSCLK low pulse width
ADSCLK high pulse width
ADSCLK to data valid hold time, V
CS rising edge to D
CS rising edge to falling edge pulse width
ADSCLK falling edge to D
ADSCLK
ADSCLK
ADSCLK
ADSCLK
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
= 32 MHz, f
= 25 MHz, f
= 24 MHz, f
= 1/f
ADSCLK
SAMPLE
SAMPLE
SAMPLE
OUT
OUT
A, D
= 2 MSPS; AV
= 1.56 MSPS; AV
= 1.5 MSPS; AV
A and D
OUT
OUT
DD
A, D
B, high impedance
= 5 V/3 V
OUT
OUT
DD
B are three-state disabled
B, high impedance
DD
= 5 V/3 V
DD
, DV
DD
, DV
, DV
DD
DD
= 5 V
DD
DD
= 2.7 V
= 3 V
= 5 V/3 V