ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 4

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
BLACKFIN PROCESSOR CORE
As shown in
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
Figure
DA1
DA0
LD1
LD0
SD
2, the Blackfin processor core contains two
32
32
32
32
32
32
R0.H
multiply, divide primitives, saturation
R7.H
R2.H
R1.H
R6.H
R5.H
R4.H
R3.H
RAB
32
R1.L
R0.L
R7.L
R6.L
R3.L
R2.L
I3
I2
R5.L
R4.L
I1
I0
32
L3
L2
L1
L0
32
BARREL
SHIFTER
B3
B2
B1
B0
8
ADDRESS ARITHMETIC UNIT
32
Rev. 0 | Page 4 of 80 | December 2010
M3
M2
M1
M0
A0
DATA ARITHMETIC UNIT
16
Figure 2. Blackfin Processor Core
40
32
DAG1
8
40
40
8
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used
to support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
DAG0
16
40
A1
ASTAT
P2
P1
P0
SP
P5
P3
FP
P4
8
32
PREG
LOOP BUFFER
SEQUENCER
DECODE
CONTROL
ALIGN
UNIT