ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 64

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
supply using the 0 to V
The common mode must be in this range to guarantee the func-
tionality of the ADC.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise free signal of amplitude –V
+V
V
– 2 V
Driving Differential Inputs
Differential operation requires that V
ously driven with two equal signals that are 180° out of phase.
The common mode must be set up externally. The common-
mode range is determined by V
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Because
not all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-to-dif-
ferential conversion.
Figure 70. Input Common-Mode Range vs. V
REF
Figure 71. Input Common-Mode Range vs. V
REF
range is used, then the input signal amplitude extends from
REF
corresponding to the digital codes of 0 to 4096. If the 2 ×
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
to +2 V
0
0
0
0
T
T
A
A
= 25°C
= 25°C
0.5
REF
after conversion.
1.0
0.5
REF
1.5
range or 2 × V
2.0
1.0
REF
V
V
REF
REF
2.5
, the power supply, and the
(V)
(V)
IN+
REF
3.0
1.5
REF
and V
REF
(0 to V
(2 × V
3.5
range, respectively.
REF
REF
IN–
4.0
Range, V
2.0
Range, V
be simultane-
Rev. 0 | Page 64 of 80 | December 2010
4.5
REF
DD
DD
5.0
2.5
= 5 V)
= 5 V)
to
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential sig-
nal to one of the analog input pairs of the ADC. The circuit
configurations illustrated in
Convert a Single-Ended Unipolar Signal Into a Differential Sig-
nal) and
Ended Bipolar Signal into a Differential Unipolar
how a dual op amp can be used to convert a single-ended signal
into a differential signal for both a bipolar and unipolar input
signal, respectively.
The voltage applied to Point A sets up the common-mode volt-
age. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a suit-
able dual op amp that can be used in this configuration to
provide differential drive to the ADC.
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in
vert a Single-Ended Unipolar Signal Into a Differential
and
Bipolar Signal into a Differential Unipolar
for dc coupling applications requiring best distortion
performance.
The circuit configuration shown in
Circuit to Convert a Single-Ended Unipolar Signal Into a Differ-
ential
differential signal.
The differential op amp driver circuit shown in
Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a
Differential Unipolar
shift a single-ended, ground-referenced (bipolar) signal to a dif-
ferential signal centered at the V
Pseudo Differential Mode
The ADC can have a total of six pseudo differential pairs. In this
mode, V
amplitude of V
V
GND
Figure 72. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
REF
Figure 73 (Dual Op Amp Circuit to Convert a Single-Ended
Signal) converts a unipolar, single-ended signal into a
IN+
Figure 73 (Dual Op Amp Circuit to Convert a Single-
2 × V
is connected to the signal source that must have an
REF
REF
p–p
440Ÿ
(or 2 × V
A
Figure 72 (Dual Op Amp Circuit to Con-
Into a Differential Signal
Signal) is configured to convert and level
220Ÿ
220Ÿ
220Ÿ
REF
V+
V–
V+
V–
Figure 72 (Dual Op Amp Circuit to
, depending on the range chosen)
1
10kŸ
ADDITIONAL PINS OMITTED FOR CLARITY.
REF
27Ÿ
27Ÿ
Figure 72 (Dual Op Amp
level of the ADC.
Signal) are optimized
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
Figure 73 (Dual
Signal) show
V
V
IN+
IN–
(D
Signal)
CAP
ADC
V
A/D
REF
1
CAP
0.47μF
B)