ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 69

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Up Times
As described in detail, the ADC has two power-down modes,
partial power-down and full power-down. This section deals
with the power-up time required when coming out of either of
these modes. It should be noted that the power-up times, as
explained in this section, apply with the recommended capaci-
tors in place on the D
To power up from full power-down, approximately 1.5 ms
should be allowed from the falling edge of CS, shown as
t
ering up from partial power-down requires much less time. The
power-up time from partial power-down is typically 1 μs; how-
ever, if using the internal reference, then the ADC must be in
partial power-down for at least 67 μs in order for this power-up
time to apply.
When power supplies are first applied to the ADC, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure the part is fully powered up before attempting a valid
conversion. Likewise, if it is intended to keep the part in the par-
tial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10
falling edge (see
second cycle, CS must be brought high before the 10
edge but after the second ADSCLK falling edge (see
(Entering Partial Power-Down
intended to place the part in full power-down mode when the
supplies are applied, then three dummy cycles must be initiated.
POWER-UP2
in
Figure 84 (Exiting Full Power-Down
ADSCLK
ADSCLK
D
D
D
D
OUT
OUT
OUT
OUT
Figure 80 (Normal Mode
CS
CS
A
B
A
B
CAP
A and D
1
1
2
Mode)). Alternatively, if it is
CAP
INVALID DATA
THE PART BEGINS
TO POWER UP.
B pins.
PARTIAL POWER DOWN.
THE PART ENTERS
Operation)); in the
INVALID DATA
th
Mode). Pow-
Rev. 0 | Page 69 of 80 | December 2010
t
Figure 83. Entering Full Power-Down Mode
ADSCLK
POWER-UP2
Figure 84. Exiting Full Power-Down Mode
Figure 81
th
10
ADSCLK
THREE-STATE
10
14
14
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
THE PART BEGINS
TO POWER UP.
The first dummy cycle must hold CS low until after the 10
ADSCLK falling edge (see
tion)); the second and third dummy cycles place the part in full
power-down (see
Mode)).
Once supplies are applied to the ADC, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final
values.
Power vs. Throughput Rate
The power consumption of the ADC varies with the throughput
rate. When using very slow throughput rates and as fast an
ADSCLK frequency as possible, the various power-down
options can be used to make significant power savings. How-
ever, the ADC quiescent current is low enough that even
without using the power-down options, there is a noticeable
variation in power consumption with sampling rate. This is true
whether a fixed ADSCLK value is used or if it is scaled with the
sampling rate.
Mode with VDD = 3
in Normal Mode with VDD = 5
throughput rate when operating in normal mode for a fixed
1
2
INVALID DATA
Figure 85 (Power vs. Throughput in Normal
1
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
Figure 83 (Entering Full Power-Down
FULL POWER DOWN.
THE PART ENTERS
V) and
VALID DATA
Figure 80 (Normal Mode Opera-
Figure 86 (Power vs. Throughput
V) show plots of power vs. the
10
THREE-STATE
14
14
th