ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 44

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Timer Cycle Timing
Table 37
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 37. Timer Cycle Timing
1
2
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
WL
WH
TIS
TIH
HTO
TOD
and
SCLK
Figure 26
Timer Pulse Width Input Low
(Measured In SCLK Cycles)
Timer Pulse Width Input High
(Measured In SCLK Cycles)
Timer Input Setup Time Before CLKOUT Low
Timer Input Hold Time After CLKOUT Low
Timer Pulse Width Output
(Measured In SCLK Cycles)
Timer Output Update Delay After CLKOUT High
/2) MHz.
TMRx OUTPUT
TMRx INPUT
CLKOUT
describe timer expired operations. The
1
1
Rev. 0 | Page 44 of 80 | December 2010
t
TIS
2
Figure 26. Timer Cycle Timing
2
t
WH
Min
1 × t
1 × t
10
–2
1 × t
,t
WL
t
TIH
SCLK
SCLK
SCLK
– 2.0
V
DDEXT
t
TOD
= 1.8 V
Max
(2
6
32
–1) × t
SCLK
t
HTO
Min
1 × t
1 × t
8
–2
1 × t
SCLK
SCLK
SCLK
V
– 1.5
DDEXT
= 2.5 V/3.3 V
Max
(2
6
32
–1) × t
SCLK
Unit
ns
ns
ns
ns
ns
ns