WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet
WM8903LGEFK/RV
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WM8903LGEFK/RV Summary of contents
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... QFN package (5x5mm) APPLICATIONS • Portable multimedia players • Multimedia handsets • Handheld gaming http://www.wolfsonmicro.com/enews WM8903 Self-clocking modes allow processor to sleep All standard sample rates from 8kHz to 96kHz Production Data, September 2010, Rev 4.0 Copyright ©2010 Wolfson Microelectronics plc ...
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WM8903 BLOCK DIAGRAM w Production Data PD, Rev 4.0, September 2010 2 ...
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Production Data DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 2 TABLE OF CONTENTS ......................................................................................... 3 PIN CONFIGURATION ........................................................................................... 6 ORDERING INFORMATION .................................................................................. 6 PIN DESCRIPTION ................................................................................................ 7 ABSOLUTE MAXIMUM RATINGS ......................................................................... 8 RECOMMENDED OPERATING CONDITIONS ..................................................... ...
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WM8903 MICBIAS CURRENT DETECT FILTERING ................................................................................................................. 38 MICROPHONE HOOK SWITCH DETECTION ............................................................................................................ 39 DIGITAL MICROPHONE INTERFACE ......................................................................... 40 ANALOGUE-TO-DIGITAL CONVERTER (ADC) .......................................................... 42 ADC DIGITAL VOLUME CONTROL ............................................................................................................................ 42 HIGH-PASS FILTER (HPF) ......................................................................................................................................... 45 ADC OVERSAMPLING RATIO (OSR) ......................................................................................................................... 46 ...
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Production Data LOOPBACK ................................................................................................................................................................. 94 CLOCKING AND SAMPLE RATES .............................................................................. 95 CLK_SYS CONTROL .................................................................................................................................................. 97 CONTROL INTERFACE CLOCKING ........................................................................................................................... 98 AUTOMATIC CLOCKING CONFIGURATION .............................................................................................................. 98 USB CLOCKING MODE ............................................................................................................................................ 100 ADC / DAC OPERATION AT 88.2K / 96K .................................................................................................................. 100 ...
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... WM8903 PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE WM8903LGEFK/V -40°C to +85°C WM8903LGEFK/RV -40°C to +85°C Note: Tube quantity = 95 Reel quantity = 3,500 w PACKAGE SENSITIVITY LEVEL 40-lead QFN (5x5x0.55mm, lead-free) 40-lead QFN (5x5x0.55mm, lead-free, tape and reel) Production Data MOISTURE PEAK SOLDERING ...
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Production Data PIN DESCRIPTION PIN NAME TYPE 1 DGND Supply Digital Input 2 MCLK 3 GPIO2/ Digital Input/Output DMIC_DAT 4 GPIO1/ Digital Input/Output DMIC_LR 5 INTERRUPT Digital Output 6 BCLK Digital Input/Output 7 DACDAT Digital Input Digital Input/Output 8 LRC ...
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WM8903 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Production Data ELECTRICAL CHARACTERISTICS TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20Hz to 20kHz. This ...
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WM8903 INPUT SIGNAL PATH Single-ended stereo line record - IN1L+IN1R pins to ADC output Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 00000b (-1.5dB) Total signal path gain = 4.45dB, incorporating 6dB single-ended to differential ...
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Production Data Single-ended stereo record from analogue microphones - IN2L / IN2R pins to ADC output Test conditions: L_MODE = R_MODE = 00b (Single ended) LIN_VOL = RIN_VOL = 11111b (+28.3dB) Total signal path gain = +34.3dB, incorporating 6dB single-ended ...
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WM8903 PGA and microphone boost PARAMETER Minimum PGA gain setting Maximum PGA gain setting Single-ended to differential conversion gain PGA gain accuracy Mute attenuation Equivalent input noise OUTPUT SIGNAL PATH Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins ...
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Production Data Stereo Playback to Line-out - DAC input to LINEOUTL+LINEOUTR pins with 3.01kΩ / 50pF load Test conditions: LINEOUTL_VOL = LINEOUTR_VOL = 111001b (0dB) PARAMETER Full Scale Output Signal Level DC offset Signal to Noise Ratio Total Harmonic Distortion ...
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WM8903 BYPASS PATH Differential stereo line input to stereo line output- IN2L-IN3L / IN2R-IN3R pins to LINEOUTL+LINEOUTR pins with 3.01kΩ / 50pF load Test conditions: L_MODE = R_MODE = 01b (Differential Line) LIN_VOL = RIN_VOL = 00101b (0dB) LINEOUTL_VOL = ...
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Production Data CHARGE PUMP PARAMETER Charge pump start-up time External component requirements To achieve specified headphone output power and performance Flyback capacitor (between CFB1 and CFB2 pins) VPOS capacitor VNEG capacitor FLL PARAMETER Input Frequency Lock time Free-running mode start-up ...
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WM8903 2. MICBIAS current detect and short circuit (Hook switch) detect functionality tested using GPIO pin rather than by interrupt. 3. Hysteresis = difference between Button Press and Button Release thresholds Digital Inputs / Outputs PARAMETER SYMBOL Input HIGH Level ...
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Production Data POWER CONSUMPTION The WM8903 power consumption is dependent on many parameters. Most significantly, it depends on supply voltages, sample rates, mode of operation, and output loading. The power consumption on each supply rail varies approximately with the square ...
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WM8903 Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 30Ω load. Test conditions DACBIAS_SEL = 01b (Normal bias x 0.5) DACVMID_BIAS_SEL = 11b (Normal bias x 0.75) PGA_BIAS = 011b (Normal bias x 0.5) CP_DYN_PWR = 1b ...
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Production Data SIGNAL TIMING REQUIREMENTS COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: • • • • Additional, specific test conditions are given within the relevant sections below. MASTER CLOCK Figure 1 Master ...
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WM8903 AUDIO INTERFACE TIMING MASTER MODE Figure 2 Audio Interface Timing – Master Mode Audio Interface Timing – Master Mode PARAMETER LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK ...
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Production Data SLAVE MODE Figure 3 Audio Interface Timing – Slave Mode Audio Interface Timing – Slave Mode PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRC set-up time to BCLK rising edge LRC hold time ...
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WM8903 TDM MODE In TDM mode important that two devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8903 ADCDAT pin tri-stating at the start and end of the data transmission is described ...
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Production Data CONTROL INTERFACE TIMING START SCLK (input SDIN Figure 5 Control Interface Timing Control Interface Timing PARAMETER SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup ...
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WM8903 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband Passband Ripple Stopband 1 Stopband 1 Attenuation Stopband 2 Stopband 2 ...
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Production Data DAC FILTER RESPONSES Figure 6 DAC Filter Response for CLK_SYS_MODE = 10b (Clock is 250 x fs related) DAC_SB_FILT = 1b (Sloping StopBand Filter) Sample Rate ≤ 24kHz Figure 8 DAC Filter Response for CLK_SYS_MODE = 10b (Clock ...
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WM8903 Figure 10 DAC Filter Response for CLK_SYS_MODE = 01b (Clock is 272 x fs related) DAC_SB_FILT = 0b (Normal Filter) Sample Rate = 88.2kHz ADC FILTER RESPONSES Figure 11 ADC Filter Response for CLK_SYS_MODE = 10b (not applicable to ...
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Production Data Figure 13 ADC Filter Passband Ripple for CLK_SYS_MODE = 10b ADC HIGH PASS FILTER RESPONSES 2.1246m -1.1717 -2.3455 -3.5193 -4.6931 -5.8669 -7.0407 -8.2145 -9.3883 -10.562 -11.736 1 2.6923 7.2484 19.515 52.54 141.45 380.83 MAGNITUDE(dB) Figure 14 ADC Digital ...
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WM8903 DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB 5000 10000 - -10 Frequency (Hz) Figure 16 De-Emphasis Digital Filter Response (32kHz) MAGNITUDE(dB 5000 10000 15000 - ...
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Production Data DEVICE DESCRIPTION INTRODUCTION The WM8903 is a high performance ultra-low power stereo CODEC optimised for portable audio applications. Flexible analogue interfaces and powerful digital signal processing (DSP) make it ideal for small portable devices. The WM8903 supports up ...
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WM8903 ANALOGUE INPUT SIGNAL PATH The WM8903 has six analogue input pins, which may be used to support connections to multiple microphone or line input sources. The input multiplexer on the Left and Right channels can be used to select ...
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Production Data INPUT PGA ENABLE The input PGAs (Programmable Gain Amplifiers) and Multiplexers are enabled using register bits INL_ENA and INR_ENA, as shown in Table 1. REGISTER ADDRESS R12 (0Ch) Power Management 0 Table 1 Input PGA Enable To enable ...
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WM8903 REGISTER ADDRESS R46 (2Eh) Analogue Left Input 1 R47 (2Fh) Analogue Right Input 1 Table 2 Input PGA Mode Selection w BIT LABEL DEFAULT 5:4 L_IP_SEL_N 00 [1:0] 3:2 L_IP_SEL_P 01 [1:0] 1:0 L_MODE [1:0] 00 5:4 R_IP_SEL_N 00 ...
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Production Data SINGLE-ENDED INPUT The Single-Ended PGA configuration is illustrated in Figure 23 for the Left channel. The available gain in this mode is from -1.57dB to +28.5dB in non-linear steps. The input impedance is 12kΩ. The input to the ...
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WM8903 DIFFERENTIAL MICROPHONE INPUT The Differential Mic PGA configuration is illustrated in Figure 25 for the Left channel. The available gain in this mode is from +12dB to +30dB in 3dB linear steps. The input impedance is 120kΩ. The input ...
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Production Data LIN_VOL [4:0], RIN_VOL [4:0] Table 4 Input PGA Volume Range w GAIN – SINGLE-ENDED MODE / DIFFERENTIAL LINE MODE 00000 -1.5 dB 00001 -1.3 dB 00010 -1.0 dB 00011 -0.7 dB 00100 -0.3 dB 00101 0.0 dB 00110 ...
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WM8903 INPUT PGA COMMON MODE AMPLIFIER In Differential Line Mode only, a Common Mode amplifier can be enabled as part of the input PGA circuit. This feature provides approximately 20dB reduction in common mode noise on the differential input, which ...
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Production Data ELECTRET CONDENSER MICROPHONE INTERFACE Electret Condenser microphones may be connected as single-ended or differential inputs to the Input PGAs described in the “Analogue Input Signal Path” section. The WM8903 provides a low-noise reference voltage suitable for biasing electret ...
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WM8903 REGISTER ADDRESS Table 7 MICBIAS Current Detect MICBIAS CURRENT DETECT FILTERING The function of the filtering is to ensure that AC current spikes caused by ambient noise conditions near the microphone do not lead to incorrect signalling of the ...
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Production Data The hook switch detection measurement frequency and the detection delay time t in the “Electrical Characteristics” section. The WM8903 Interrupt function is described in the “Interrupts” section. Example control sequences for configuring the Interrupts functions for MICBIAS current ...
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WM8903 In applications where the Current Detect threshold is close to the level of the current spikes, the probability of false detections is reduced by the hysteresis and digital filtering described above. Note that the filtering algorithm provides only limited ...
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Production Data Figure 28 Digital Microphone Interface Control When GPIO1 is configured as DMIC_LR Clock output, the WM8903 outputs a clock which supports Digital Mic operation at a multiple of the ADC sampling rate, in the range 1-3MHz. The ADC ...
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WM8903 REGISTER ADDRESS R164 (A4h) Clock Rate Test 4 Table 9 Digital Microphone Interface Control Note that, in addition to setting the ADC_DIG_MIC bit as described in Table 9, the pins GPIO1/DMIC_LR and GPIO2/DMIC_DAT must also be configured to provide ...
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Production Data REGISTER ADDRESS R36 (24h) ADC Digital Volume Left R37 (25h) ADC Digital Volume Right Table 11 ADC Digital Volume Control w BIT LABEL DEFAULT 8 ADCVU N/A 7:0 ADCL_VOL [7:0] 1100_0000 (0dB) 8 ADCVU N/A 7:0 ADCR_VOL [7:0] ...
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WM8903 ADCL_VOL or ADCR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 ...
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Production Data HIGH-PASS FILTER (HPF) A digital high-pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in handheld applications (e.g. wind noise, handling noise ...
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WM8903 ADC OVERSAMPLING RATIO (OSR) The ADC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is high for best performance; using the lower OSR setting reduces ADC power consumption. REGISTER ADDRESS R10 ...
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Production Data Figure 30 DRC Compression Characteristic The slope of R0 and R1 are determined by register fields DRC_R0_SLOPE_COMP and DRC_R1_SLOPE_COMP respectively. A slope of 1 indicates constant gain in this region. A slope less than 1 represents compression (i.e. ...
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WM8903 REGISTER ADDRESS R42 (2Ah) DRC 2 R43 (2Bh) DRC 3 Table 17 DRC Compression Control GAIN LIMITS The minimum and maximum gain applied by the DRC is set by register fields DRC_MINGAIN and DRC_MAXGAIN. These limits can be used ...
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Production Data REGISTER ADDRESS R41(29h) DRC 1 Table 18 DRC Gain Limits DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over a ...
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WM8903 Note: For detailed information about DRC attack and decay rates, please see Wolfson application note WAN0247. ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a ...
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Production Data REGISTER ADDRESS R40 (28h) DRC 0 R41 (29h) DRC 1 Table 21 DRC Quick-Release Control GAIN SMOOTHING The DRC includes a gain smoothing filter in order to prevent gain ripples. A programmable level of hysteresis is also used ...
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WM8903 INITIALISATION When the DRC is initialised, the gain is set to the level determined by the DRC_STARTUP_GAIN register field. The default setting is 0dB, but values from -18dB to +36dB are available, as described in Table 23. REGISTER ADDRESS ...
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Production Data DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right ...
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WM8903 The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left and ...
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Production Data REGISTER ADDRESS R24 (18h) Audio Interface 0 Table 26 DAC Interface Volume Boost DIGITAL SIDETONE Digital sidetone mixing (from ADC output into DAC input) is available when ADCs and DACs are operating at the same sample rate. Digital ...
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WM8903 The digital sidetone volume settings are shown in Table 28. Table 28 Digital Sidetone Volume DIGITAL-TO-ANALOGUE CONVERTER (DAC) The WM8903 DACs receive digital input data from the DACDAT pin and via the digital sidetone path (see “Digital Mixing” section). ...
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Production Data REGISTER ADDRESS R30 (1Eh) DAC Digital Volume Left R31 (1Fh) DAC Digital Volume Right Table 30 DAC Digital Volume Control w BIT LABEL DEFAULT 8 DACVU N/A 7:0 DACL_VOL [7:0] 1100_0000 (0dB) 8 DACVU N/A 7:0 DACR_VOL [7:0] ...
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WM8903 DACL_VOL or DACR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 ...
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Production Data DAC SOFT MUTE AND SOFT UN-MUTE The WM8903 has a soft mute function. When enabled, this gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to ...
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WM8903 REGISTER ADDRESS R33 (21h) DAC Digital 1 Table 32 DAC Soft-Mute Control DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on whichever DAC is enabled. ...
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Production Data DAC SLOPING STOPBAND FILTER Two DAC filter types are available, selected by the register bit DAC_SB_FILT. When operating at sample rates <= 24kHz (e.g. during voice communication recommended that the sloping stopband filter type is selected ...
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WM8903 DAC OVERSAMPLING RATIO (OSR) The DAC oversampling rate is programmable to allow power consumption versus audio performance trade-offs. The default oversampling rate is low for reduced power consumption; using the higher OSR setting improves the DAC signal-to-noise performance. REGISTER ...
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Production Data OUTPUT SIGNAL PATH The outputs HPOUTL and LINEOUTL are derived from the Left Mixer, whilst the HPOUTR and LINEOUTR are derived from the Right Mixer. These mixers allow the stereo DAC and stereo bypass signals to be mixed ...
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WM8903 OUTPUT SIGNAL PATHS ENABLE The output mixers and drivers can be independently enabled and disabled using the register bits described in Table 38. Note that the Headphone Outputs and Line Outputs are also controlled by fields located within Register ...
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Production Data HEADPHONE / LINE OUTPUT SIGNAL PATHS ENABLE The Headphone / Line output paths can be actively discharged to AGND through internal resistors if desired. This is desirable at start-up in order to achieve a known output stage condition ...
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WM8903 REGISTER ADDRESS w BIT LABEL DEFAULT 5 HPL_ENA_DLY 0 HPL_ENA HPR_RMV_SHO HPR_ENA_OUTP 0 HPR_ENA_DLY 1 0 HPR_ENA 0 0 Production Data DESCRIPTION Enables HPL intermediate stage 0 = Disabled 1 = Enabled For ...
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Production Data REGISTER ADDRESS R94 (5Eh) Analogue Lineout 0 Table 41 Headphone / Line Output Pop Suppression Control w BIT LABEL DEFAULT 7 LINEOUTL_RMV 0 _SHORT 6 LINEOUTL_ENA_ 0 OUTP 5 LINEOUTL_ENA_ 0 DLY 4 LINEOUTL_ENA 0 3 LINEOUTR_RMV 0 ...
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WM8903 OUTPUT PGA BIAS CONTROL The output PGA circuits use the Master bias current (see “Reference Voltages and Master Bias”). The output PGA bias currents can also be controlled using the PGA_BIAS field as described in Table 42. Selecting a ...
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Production Data OUTPUT MIXER CONTROL Each of the four output mixers has the same four inputs: • DAC Left • DAC Right • Bypass Left • Bypass Right The input signals to the left and right mixers (feeding HPOUTL/R and ...
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WM8903 The input signals to the speaker mixers are enabled and controlled using the register fields described in Table 45. These mixers provide a selectable 0dB or -6dB volume control on each input. The input signals may also be controlled ...
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Production Data REGISTER ADDRESS R55 (37h) Analogue Spk Mix Right 1 Table 45 Speaker Mixer Control OUTPUT VOLUME CONTROL Each analogue output can be independently controlled. The headphone output control fields are described in Table 46. The line output control ...
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WM8903 REGISTER ADDRESS R57 (39h) Analogue OUT1 Left R58 (3Ah) Analogue OUT1 Right Table 46 Volume Control for HPOUTL and HPOUTR w BIT LABEL DEFAULT 8 HPL_MUTE 0 7 HPOUTVU 0 HPOUTLZC 6 0 5:0 HPOUTL_VOL 10_1101 [5:0] HPR_MUTE 8 ...
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Production Data REGISTER ADDRESS R59 (3Bh) Analogue OUT2 Left R60 (3Ch) Analogue OUT2 Right Table 47 Volume Control for LINEOUTL and LINEOUTR w BIT LABEL DEFAULT 8 LINEOUTL_MUTE 0 7 LINEOUTVU 0 LINEOUTLZC 6 0 5:0 LINEOUTL_VOL 11_1001 [5:0] 8 ...
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WM8903 REGISTER ADDRESS R62 (3Eh) Analogue OUT3 Left R63 (3Fh) Analogue OUT3 Right Table 48 Volume Control for LON/LOP and RON/ROP w BIT LABEL DEFAULT 8 SPKL_MUTE 1 7 SPKVU 0 SPKLZC 6 0 5:0 SPKL_VOL [5:0] 11_1001 8 SPKR_MUTE ...
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Production Data ANALOGUE OUTPUTS The WM8903 has eight analogue output pins: • Headphone outputs, HPOUTL and HPOUTR • Line outputs, LINEOUTL and LINEOUTR • Differential line outputs, LON/LOP and RON/ROP The output signal paths and associated control registers are illustrated ...
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WM8903 EXTERNAL COMPONENTS FOR GROUND-REFERENCED OUTPUTS In the case of the ground referenced outputs HPOUTL, HPOUTR, LINEOUTL and LINEOUTR recommended to connect a zobel network to the audio output pins for best audio performance in all applications. The ...
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Production Data REFERENCE VOLTAGES AND MASTER BIAS This section describes the analogue reference voltage and bias current controls. It also describes the VMID soft-start circuit for pop-free start-up and shut-down. Note that, under the recommended usage conditions of the WM8903, ...
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WM8903 A pop-suppressed start-up requires VMID to be enabled smoothly, without the step change normally associated with the initial stage of the VMID capacitor charging. A pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal ...
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Production Data POP SUPPRESSION CONTROL The WM8903 incorporates Wolfson’s SilentSwitch™ technology which enables pops normally associated with Start-Up, Shut-Down or signal path control to be suppressed. To achieve maximum benefit from these features, careful attention is required to the sequence ...
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WM8903 CHARGE PUMP The WM8903 incorporates a dual-mode Charge Pump which generates the supply rails for the headphone and line output drivers, HPOUTL, HPOUTR, and LINEOUTL and LINEOUTR. The Charge Pump has a single supply input, CPVDD, and generates split ...
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Production Data The Charge Pump control fields are described in Table 53. REGISTER ADDRESS R98 (62h) Charge Pump 0 R104 (68h) Class W 0 Table 53 Charge Pump Control DC SERVO The WM8903 provides a DC servo circuit on the ...
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WM8903 REGISTER ADDRESS R67 (43h) DC Servo 0 R69 (45h) DC Servo 2 Table 54 DC Servo Control To reduce power consumption when unused audio outputs are disabled, the DC Servo correction should also be disabled. The WM8903 provides the ...
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Production Data REGISTER ADDRESS R71 (47h) DC Servo 4 R72 (48h) DC Servo 5 R73 (49h) DC Servo 6 R74 (4Ah) DC Servo 7 R81 (51h) DC Servo Readback 1 R82 (52h) DC Servo Readback 2 R83 (53h) DC Servo ...
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WM8903 DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data into the WM8903 and outputting ADC data from it. The digital audio interface uses four pins: • ADCDAT: ADC data output • DACDAT: DAC data input ...
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Production Data The direction of these signals and the clock frequencies are controlled as described in the “Digital Audio Interface Control” section. BCLK and LRC can be enabled as outputs in Slave mode, allowing mixed Master/Slave operation - see “Digital ...
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WM8903 BCLK FREQUENCY The BCLK frequency is controlled relative to CLK_SYS by the BCLK_DIV divider. Internal clock divide and phase control mechanisms ensure that the BCLK and LRC edges will occur in a predictable and repeatable position relative to each ...
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Production Data LRC BCLK DACDAT/ ADCDAT Figure 43 I2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1 edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of ...
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WM8903 Figure 46 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) Figure 47 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. WM8903 ADC data that is output on the Left Channel will ...
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Production Data Figure 48 TDM in Right-Justified Mode Figure 49 TDM in Left-Justified Mode Figure 50 TDM in I LRC BCLK DACDAT/ ADCDAT Figure 51 TDM in DSP Mode Mode 1/fs Falling edge can occur anywhere ...
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WM8903 Figure 52 TDM in DSP Mode B DIGITAL AUDIO INTERFACE CONTROL The register bits controlling audio data format, word length left/right channel data source and TDM are summarised in Table 56. REGISTER ADDRESS R24 (18h) Audio Interface 0 R25 ...
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Production Data REGISTER ADDRESS R38 (26h) ADC Digital 0 Table 56 Digital Audio Interface Data Control Note that the WM8903 is a 24-bit device. In 32-bit mode (AIF_WL=11), the 8 LSBs are ignored on the receiving side and not driven ...
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WM8903 When the BCLK pin is an output (BCLK_DIR=1), BCLK is derived from the internal CLK_SYS signal (see “Clocking and Sample Rates”). In this case, the BCLK frequency is controlled in relation to CLK_SYS by the BCLK_DIV register field. When ...
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Production Data COMPANDING The WM8903 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 58. REGISTER ADDRESS R24 (18h) Audio Interface 0 Table 58 Companding Control Companding uses a piecewise linear approximation ...
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WM8903 120 100 Figure 53 μ-Law Companding 120 100 Figure 54 A-Law Companding LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set, the ADC digital data output is routed to the ...
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Production Data Note: When the digital sidetone is enabled, ADC data will continue to be added to DAC data when loopback is enabled. CLOCKING AND SAMPLE RATES The WM8903 supports a wide range of standard audio sample rates from 8kHz ...
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WM8903 Figure 55 Clocking Overview w Production Data PD, Rev 4.0, September 2010 96 ...
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Production Data CLK_SYS CONTROL The CLK_SRC_SEL bit is used to select the source for CLK_SYS. The source may be either the MCLK input or the FLL output. The selected source may be adjusted by the MCLKDIV2 divider to generate CLK_SYS. ...
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WM8903 The CLK_SYS control register fields are defined in Table 61. REGISTER ADDRESS R20 (14h) Clock Rates 0 R21 (15h) Clock Rates 1 R22 (16h) Clock Rates 2 R108 (6Ch) Write Sequencer 0 Table 61 MCLK and CLK_SYS Control CONTROL ...
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Production Data The DSP clocking is enabled by CLK_DSP_ENA; see Table 61 for details of this register. REGISTER ADDRESS R21 (15h) Clock Rates 1 Table 62 Automatic Clocking Configuration Control Table 63 Sample Rate Decoder Control The clock division ratios ...
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WM8903 USB CLOCKING MODE The clock division ratios with CLK_SYS_MODE = 01 or CLK_SYS_MODE = 10 allow compatibility with a 12MHz USB clock, at sample rates up to 48kHz. For example, with a 12MHz (USB) clock and 8kHz sample rate, ...
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Production Data DIGITAL MICROPHONE (DMIC) OPERATION When GPIO1/DMIC_LR is configured as DMIC_LR Clock output, the WM8903 outputs a clock which supports Digital Microphone operation at a multiple of the ADC sampling rate. The precise clock frequency varies according to the ...
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WM8903 If low power consumption is required, then FLL settings must be chosen when N integer (ie. FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0. For best FLL performance, ...
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Production Data See Table 69 for the coding of the FLL_OUTDIV and FLL_FRATIO fields. Note that F In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field. This field is coded as ...
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WM8903 REGISTER ADDRESS R130 (82h) FLL Control 3 R131 (83h) FLL Control 4 Table 69 FLL Register Map w BIT LABEL DEFAULT 10:9 FLL_CLK_REF 00 _DIV [1:0] FLL_CTRL_RA 8:6 000 TE [2:0] 5:3 FLL_OUTDIV 000 [2:0] FLL_FRATIO 2:0 000 [2:0] ...
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Production Data FREE-RUNNING FLL CLOCK The FLL can generate a clock signal even when the external reference is removed. It should be noted that the accuracy of this clock is reduced, and a reference source should always be used where ...
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WM8903 EXAMPLE FLL SETTINGS Table 70 provides example FLL settings for generating common CLK_SYS frequencies from a variety of low and high frequency reference inputs FLL_CLK_ REF OUT REF_DIV 32.000 12.288 Divide by 1 kHz MHz (0h) 32.000 ...
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Production Data GENERAL PURPOSE INPUT/OUTPUT (GPIO) The WM8903 provides five multi-function pins which can be configured to provide a number of different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins are: • GPIO1/DMIC_LR • ...
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WM8903 Interrupt Output is the default function of GPIO4. See “Interrupts” for further details. BCLK is the default function of GPIO5. This may be input or output. Note that, when BCLK is enabled on this pin (GP5_FN = 1h), the ...
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Production Data REGISTER ADDRESS R117 (75h) GPIO Control 2 R118 (76h) GPIO Control 3 w BIT LABEL DEFAULT 13:8 GP2_FN [5:0] 00_0000 7 GP2_DIR 1 6 GP2_OP_CFG 0 5 GP2_IP_CFG 1 4 GP2_LVL 0 GP2_PD 3 1 GP2_PU 2 0 ...
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WM8903 REGISTER ADDRESS R119 (77h) GPIO Control 4 w BIT LABEL DEFAULT 6 GP3_OP_CFG 0 GP3_IP_CFG GP3_LVL 0 3 GP3_PD 1 2 GP3_PU 0 1 GP3_INTMODE 0 GP3_DB 0 0 13:8 GP4_FN [5:0] 00_0010 GP4_DIR 7 0 ...
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Production Data REGISTER ADDRESS R120 (78h) GPIO Control 5 Table 72 GPIO Control w BIT LABEL DEFAULT 1 GP4_INTMODE 0 GP4_DB 0 0 13:8 GP5_FN [5:0] 00_0001 GP5_DIR GP5_OP_CFG 0 5 GP5_IP_CFG 1 4 GP5_LVL 0 3 ...
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WM8903 INTERRUPTS The Interrupt Controller has multiple inputs. These include the GPIO input pins and the MICBIAS current detection circuits. Any combination of these inputs can be used to trigger an Interrupt (IRQ) event. There is an Interrupt Status field ...
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Production Data REGISTER ADDRESS R121 (79h) Interrupt Status 1 R122 (7Ah) Interrupt Status 1 Mask w BIT LABEL DEFAULT 15 MICSHRT_EINT 0 14 MICDET_EINT 0 13 WSEQ_BUSY_E 0 INT 5 FLL_LOCK_EIN GP5_EINT 0 3 GP4_EINT 0 2 ...
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WM8903 REGISTER ADDRESS R123 (7Bh) Interrupt Polarity 1 R126 (7Eh) Interrupt Control Table 73 Interrupt Control w BIT LABEL DEFAULT 1 IM_GP2_EINT 1 0 IM_GP1_EINT 1 15 MICSHRT_INV 0 14 MICDET_INV 0 5 FLL_LOCK_INV 0 0 IRQ_POL 0 Production Data ...
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Production Data CONTROL INTERFACE The WM8903 is controlled by writing to registers through a 2-wire serial control interface. Readback is available for all registers, including Chip ID, power management status and GPIO status. Note that cannot be assured ...
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WM8903 SCLK SDIN D7 D1 R/W (Write) START device ID ACK Figure 57 Control Interface Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 58. Figure 58 Control Interface Register Read The ...
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Production Data Figure 60 Single Register Read from Specified Address Figure 61 Multiple Register Write to Specified Address using Auto-increment Figure 62 Multiple Register Read from Specified Address using Auto-increment Figure 63 Multiple Register Read from Last Address using Auto-increment ...
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WM8903 CONTROL WRITE SEQUENCER The Control Write Sequencer is a programmable unit that forms part of the WM8903 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the ...
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Production Data REGISTER ADDRESS R108 (6Ch) Write Sequencer 0 R111 (6Fh) Write Sequencer 3 R112 (70h) Write Sequencer 4 Table 76 Write Sequencer Control – Initiating a Sequence PROGRAMMING A SEQUENCE A sequence consists of write operations to data bits ...
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WM8903 WSEQ_DATA_WIDTH is a 3-bit field which identifies the width of the data block to be written. This enables selected portions of a Control Register to be updated without any concern for other bits within the same register, eliminating the ...
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Production Data Note that a ‘Dummy’ write can be inserted into a control sequence by commanding the sequencer to write a value bit 0 of Register R255 (FFh). This is effectively a write to a non-existent register ...
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WM8903 Index addresses may be programmed to users’ own settings at any time, as described in “Programming a Sequence” Users’ own settings remain in memory and are not affected by software resets (i.e. writing to Register R0). ...
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Production Data WSEQ REGISTER WIDTH INDEX ADDRESS 13 (0Dh) R18 (12h) 2 bits 14 (0Eh) R255 (FFh) 1 bit 15 (0Fh) R4 (04h) 1 bit 16 (10h) R98 (62h) 1 bit 17 (11h) R255 (FFh) 1 bit 18 (12h) R90 ...
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WM8903 SHUTDOWN SEQUENCE The Shutdown sequence is initiated by writing 0120h to Register R111 (6Fh). This single operation starts the Control Write Sequencer at Index Address 32 (20h) and executes the sequence defined in Table 80. For typical clocking configurations ...
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Production Data WSEQ REGISTER WIDTH INDEX ADDRESS 47 (2Fh) R5 (05h) 8 bits 48 (30h) R4 (04h) 2 bits Table 80 Shutdown Sequence w START DATA DELAY EOS Bit 0 00h 0h 0b Bit 0 00h 0h 1b WM8903 DESCRIPTION ...
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WM8903 POWER-ON RESET The WM8903 includes an internal Power-On-Reset (POR) circuit, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. The internal POR thresholds. ...
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Production Data The POR ¯ ¯ ¯ threshold has been exceeded, POR writes to the control interface are ignored. Once AVDD and DCVDD have reached their respective power on thresholds, POR control interface may take place. Note that a minimum ...
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WM8903 QUICK START-UP AND SHUTDOWN The WM8903 has the capability to perform a quick start-up and shut-down with a minimum number of register operations. This is achieved using the Control Write Sequencer, which is configured with default start-up settings that ...
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Production Data SOFTWARE RESET AND CHIP ID A Software Reset can be commanded by writing to Register R0. This is a read-only register field and the contents will not be affected by writing to this Register. The Chip ID can ...
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WM8903 REGISTER MAP w Production Data PD, Rev 4.0, September 2010 130 ...
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Production Data w WM8903 PD, Rev 4.0, September 2010 131 ...
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WM8903 w Production Data PD, Rev 4.0, September 2010 132 ...
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Production Data REGISTER BITS BY ADDRESS REGISTER BIT LABEL ADDRESS R0 (00h) 15:0 SW_RST_DEV_ID1 SW Reset [15:0] and ID Register 00h SW Reset and ID REGISTER BIT LABEL ADDRESS R1 (01h) 3:0 CHIP_REV [3:0] Revision Number Register 01h Revision Number ...
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WM8903 REGISTER BIT LABEL ADDRESS R5 (05h) 7 VMID_TIE_ENA VMID Control 0 6 BUFIO_ENA 5 VMID_IO_ENA 4:3 VMID_SOFT [1:0] 2:1 VMID_RES [1:0] 0 VMID_BUF_EN A Register 05h VMID Control 0 REGISTER BIT LABEL ADDRESS R6 (06h) Mic 5:4 MICDET_THR [1:0] ...
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Production Data REGISTER BIT LABEL ADDRESS R8 (08h) 5 DAC_BIAS_BOOST Analogue DAC 0 4:3 DACBIAS_SEL [1:0] 2:1 DACVMID_BIAS_SEL [1:0] Register 08h Analogue DAC 0 REGISTER BIT LABEL ADDRESS R10 (0Ah) 0 ADC_OSR128 Analogue ADC 0 Register 10h Analogue ADC 0 ...
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WM8903 REGISTER BIT LABEL ADDRESS R14 (0Eh) 1 HPL_PGA_ENA Power Management 2 0 HPR_PGA_ENA Register 0Eh Power Management 2 REGISTER BIT LABEL ADDRESS R15 (0Fh) 1 LINEOUTL_PGA_ENA Power Management 3 0 LINEOUTR_PGA_EN A Register 0Fh Power Management 3 REGISTER BIT ...
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Production Data REGISTER BIT LABEL ADDRESS R18 (12h) 3 DACL_ENA Power Management 6 2 DACR_ENA 1 ADCL_ENA 0 ADCR_ENA Register 12h Power Management 6 REGISTER BIT LABEL ADDRESS R20 (14h) 0 MCLKDIV2 Clock Rates 0 Register 14h Clock Rates 0 ...
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WM8903 REGISTER BIT LABEL ADDRESS 9:8 CLK_SYS_MODE [1:0] 3:0 SAMPLE_RATE [3:0] Register 15h Clock Rates 1 w DEFAULT DESCRIPTION 0111 = 1088 *fs 1000 = 1496*fs 1001 = 1632*fs 1010 to 1111 = Reserved if CLK_SYS_MODE = 10 (250*fs related ...
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Production Data REGISTER BIT LABEL ADDRESS R22 (16h) 2 CLK_SYS_ENA Clock Rates 2 1 CLK_DSP_ENA 0 TO_ENA Register 16h Clock Rates 2 REGISTER BIT LABEL ADDRESS R24 (18h) 12 DACL_DATINV Audio Interface 0 11 DACR_DATINV 10:9 DAC_BOOST [1:0] 8 LOOPBACK ...
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WM8903 REGISTER BIT LABEL ADDRESS R25 (19h) 13 AIFDAC_TDM Audio Interface 1 12 AIFDAC_TDM_CHAN 11 AIFADC_TDM 10 AIFADC_TDM_CHAN 9 LRCLK_DIR 7 AIF_BCLK_INV 6 BCLK_DIR 4 AIF_LRCLK_INV 3:2 AIF_WL [1:0] 1:0 AIF_FMT [1:0] Register 19h Audio Interface 1 w DEFAULT DESCRIPTION ...
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Production Data REGISTER BIT LABEL ADDRESS R26 (1Ah) 4:0 BCLK_DIV [4:0] Audio Interface 2 Register 1Ah Audio Interface 2 REGISTER BIT LABEL ADDRESS R27 (1Bh) 10:0 LRCLK_RATE Audio [10:0] Interface 3 Register 1Bh Audio Interface 3 REGISTER BIT LABEL ADDRESS ...
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WM8903 REGISTER BIT LABEL ADDRESS R31 (1Fh) 8 DACVU DAC Digital Volume Right 7:0 DACR_VOL [7:0] Register 1Fh DAC Digital Volume Right REGISTER BIT LABEL ADDRESS R32 (20h) 11:8 ADCL_DAC_SVOL DAC Digital [3:0] 0 7:4 ADCR_DAC_SVOL [3:0] 3:2 ADC_TO_DACL [1:0] ...
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Production Data REGISTER BIT LABEL ADDRESS R33 (21h) 12 DAC_MONO DAC Digital 1 11 DAC_SB_FILT 10 DAC_MUTERATE 9 DAC_MUTEMODE 3 DAC_MUTE 2:1 DEEMPH [1:0] 0 DAC_OSR Register 21h DAC Digital 1 REGISTER BIT LABEL ADDRESS R36 (24h) 8 ADCVU ADC ...
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WM8903 REGISTER BIT LABEL ADDRESS R37 (25h) 8 ADCVU ADC Digital Volume Right 7:0 ADCR_VOL [7:0] Register 25h ADC Digital Volume Right REGISTER BIT LABEL ADDRESS R38 (26h) 6:5 ADC_HPF_CUT ADC Digital [1: ADC_HPF_ENA 1 ADCL_DATINV 0 ADCR_DATINV ...
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Production Data REGISTER BIT LABEL ADDRESS R40 (28h) 15 DRC_ENA DRC 0 12:11 DRC_THRESH_HYST [1:0] 10:6 DRC_STARTUP_GAIN [4:0] 5 DRC_FF_DELAY 3 DRC_SMOOTH_ENA 2 DRC_QR_ENA 1 DRC_ANTICLIP_ENA 0 DRC_HYST_ENA Register 28h DRC 0 w DEFAULT DESCRIPTION DRC enable ...
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WM8903 REGISTER BIT LABEL ADDRESS R41 (29h) 15:12 DRC_ATTACK_RATE DRC 1 [3:0] 11:8 DRC_DECAY_RATE [3:0] 7:6 DRC_THRESH_QR [1:0] 5:4 DRC_RATE_QR [1:0] 3:2 DRC_MINGAIN [1:0] 1:0 DRC_MAXGAIN [1:0] Register 29h DRC 1 w DEFAULT DESCRIPTION Gain attack rate (seconds/6dB) 0011 0000 ...
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Production Data REGISTER BIT LABEL ADDRESS R42 (2Ah) 5:3 DRC_R0_SLOPE_COMP DRC 2 [2:0] 2:0 DRC_R1_SLOPE_COMP [2:0] Register 2Ah DRC 2 REGISTER BIT LABEL ADDRESS R43 (2Bh) 10:5 DRC_THRESH_COMP DRC 3 [5:0] 4:0 DRC_AMP_COMP [4:0] Register 2Bh DRC 3 w DEFAULT ...
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WM8903 REGISTER BIT LABEL ADDRESS R44 (2Ch) 7 LINMUTE Analogue Left Input 0 4:0 LIN_VOL [4:0] Register 2Ch Analogue Left Input 0 w DEFAULT DESCRIPTION Left Input PGA Mute not muted 1 = muted 0_0101 Left Input ...
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Production Data REGISTER BIT LABEL ADDRESS R45 (2Dh) 7 RINMUTE Analogue Right Input 0 4:0 RIN_VOL [4:0] Register 2Dh Analogue Right Input 0 w DEFAULT DESCRIPTION Right Input PGA Mute not muted 1 = muted 0_0101 Right ...
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WM8903 REGISTER BIT LABEL ADDRESS R46 (2Eh) 6 INL_CM_ENA Analogue Left Input 1 5:4 L_IP_SEL_N [1:0] 3:2 L_IP_SEL_P [1:0] 1:0 L_MODE [1:0] Register 2Eh Analogue Left Input 1 REGISTER BIT LABEL ADDRESS R47 (2Fh) 6 INR_CM_ENA Analogue Right Input 1 ...
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Production Data REGISTER BIT LABEL ADDRESS 1:0 R_MODE [1:0] Register 2Fh Analogue Right Input 1 REGISTER BIT LABEL ADDRESS R50 (32h) 3 DACL_TO_MIXOUTL Analogue Left Mix 0 2 DACR_TO_MIXOUTL 1 BYPASSL_TO_MIXOUTL 0 BYPASSR_TO_MIXOUT L Register 32h Analogue Left Mix 0 ...
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WM8903 REGISTER BIT LABEL ADDRESS R52 (34h) 3 DACL_TO_MIXSPKL Analogue Spk Mix Left 0 2 DACR_TO_MIXSPKL 1 BYPASSL_TO_MIXSPKL 0 BYPASSR_TO_MIXSPK L Register 34h Analogue Spk Mix Left 0 REGISTER BIT LABEL ADDRESS R53 (35h) 3 DACL_MIXSPKL_VOL Analogue Spk Mix Left ...
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Production Data REGISTER BIT LABEL ADDRESS R55 (37h) 3 DACL_MIXSPKR_VOL Analogue Spk Mix Right 1 2 DACR_MIXSPKR_VOL 1 BYPASSL_MIXSPKR_VOL 0 BYPASSR_MIXSPKR_VO L Register 37h Analogue Spk Mix Right 1 REGISTER BIT LABEL ADDRESS R57 (39h) 8 HPL_MUTE Analogue OUT1 Left ...
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WM8903 REGISTER BIT LABEL ADDRESS 5:0 HPOUTR_VOL [5:0] Register 3Ah Analogue OUT1 Right REGISTER BIT LABEL ADDRESS R59 (3Bh) 8 LINEOUTL_MUTE Analogue OUT2 Left 7 LINEOUTVU 6 LINEOUTLZC 5:0 LINEOUTL_VOL [5:0] Register 3Bh Analogue OUT2 Left REGISTER BIT LABEL ADDRESS ...
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Production Data REGISTER BIT LABEL ADDRESS R62 (3Eh) 8 SPKL_MUTE Analogue OUT3 Left 7 SPKVU 6 SPKLZC 5:0 SPKL_VOL [5:0] Register 3Eh Analogue OUT3 Left REGISTER BIT LABEL ADDRESS R63 (3Fh) 8 SPKR_MUTE Analogue OUT3 Right 7 SPKVU 6 SPKRZC ...
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WM8903 REGISTER BIT LABEL ADDRESS R65 (41h) 1 SPK_DISCHARGE Analogue SPK Output Control 0 0 VROI Register 41h Analogue SPK Output Control 0 REGISTER BIT LABEL ADDRESS R67 (43h) 4 DCS_MASTER_EN DC Servo 0 A 3:0 DCS_ENA [3:0] Register 43h ...
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Production Data REGISTER BIT LABEL ADDRESS R73 (49h) DCS_LOUTL_WRITE_VA 7:0 DC Servo 6 L [7:0] Register 49h DC Servo 6 REGISTER BIT LABEL ADDRESS R74 (4Ah) 7:0 DCS_LOUTR_WRITE_VA DC Servo 7 L [7:0] Register 4Ah DC Servo 7 REGISTER BIT ...
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WM8903 REGISTER BIT LABEL ADDRESS R84 (54h) DCS_LOUTR_INTEG [7:0] 7:0 DC Servo Readback 4 Register 54h DC Servo Readback 4 REGISTER BIT LABEL ADDRESS R90 (5Ah) 7 HPL_RMV_SHORT Analogue HPL_ENA_OUTP 5 HPL_ENA_DLY 4 HPL_ENA 3 HPR_RMV_SHORT 2 ...
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Production Data REGISTER BIT LABEL ADDRESS 0 HPR_ENA Register 5Ah Analogue HP 0 REGISTER BIT LABEL ADDRESS R94 (5Eh) 7 LINEOUTL_RMV_SHORT Analogue Lineout 0 6 LINEOUTL_ENA_OUTP 5 LINEOUTL_ENA_DLY 4 LINEOUTL_ENA 3 LINEOUTR_RMV_SHOR T 2 LINEOUTR_ENA_OUTP 1 LINEOUTR_ENA_DLY w DEFAULT DESCRIPTION ...
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WM8903 REGISTER BIT LABEL ADDRESS 0 LINEOUTR_ENA Register 5Eh Analogue Lineout 0 REGISTER BIT LABEL ADDRESS R98 (62h) 0 CP_ENA Charge Pump 0 Register 62h Charge Pump 0 REGISTER BIT LABEL ADDRESS R104 (68h) 0 CP_DYN_PWR Class W 0 Register ...
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Production Data REGISTER BIT LABEL ADDRESS 11:8 WSEQ_DATA_START [3:0] 7:0 WSEQ_ADDR [7:0] Register 6Dh Write Sequencer 1 REGISTER BIT LABEL ADDRESS R110 (6Eh) 14 WSEQ_EOS Write Sequencer 2 11:8 WSEQ_DELAY [3:0] 7:0 WSEQ_DATA [7:0] 0000_0000 Data to be written in ...
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WM8903 REGISTER BIT LABEL ADDRESS R112 (70h) 9:4 WSEQ_CURRENT_INDEX Write [5:0] Sequencer 4 0 WSEQ_BUSY Register 70h Write Sequencer 4 REGISTER BIT LABEL ADDRESS R116 (74h) 13:8 GP1_FN [5:0] GPIO Control 1 7 GP1_DIR 6 GP1_OP_CFG 5 GP1_IP_CFG 4 GP1_LVL ...
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Production Data REGISTER BIT LABEL ADDRESS R117 (75h) 13:8 GP2_FN [5:0] GPIO Control 2 7 GP2_DIR 6 GP2_OP_CFG 5 GP2_IP_CFG 4 GP2_LVL 3 GP2_PD 2 GP2_PU 1 GP2_INTMODE 0 GP2_DB Register 75h GPIO Control 2 w DEFAULT DESCRIPTION GPIO 2 ...
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WM8903 REGISTER BIT LABEL ADDRESS R118 (76h) 13:8 GP3_FN [5:0] GPIO Control 3 7 GP3_DIR 6 GP3_OP_CFG 5 GP3_IP_CFG 4 GP3_LVL 3 GP3_PD 2 GP3_PU 1 GP3_INTMODE 0 GP3_DB Register 76h GPIO Control 3 w DEFAULT DESCRIPTION GPIO 3 Pin ...
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Production Data REGISTER BIT LABEL ADDRESS R119 (77h) 13:8 GP4_FN [5:0] GPIO Control 4 7 GP4_DIR 6 GP4_OP_CFG 5 GP4_IP_CFG 4 GP4_LVL 3 GP4_PD 2 GP4_PU 1 GP4_INTMODE 0 GP4_DB Register 77h GPIO Control 4 w DEFAULT DESCRIPTION GPIO 4 ...
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WM8903 REGISTER BIT LABEL ADDRESS R120 (78h) 13:8 GP5_FN [5:0] GPIO Control 5 7 GP5_DIR 6 GP5_OP_CFG 5 GP5_IP_CFG 4 GP5_LVL 3 GP5_PD 2 GP5_PU 1 GP5_INTMODE 0 GP5_DB Register 78h GPIO Control 5 w DEFAULT DESCRIPTION GPIO 5 Pin ...
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Production Data REGISTER BIT LABEL ADDRESS R121 (79h) 15 MICSHRT_EINT Interrupt Status 1 14 MICDET_EINT 13 WSEQ_BUSY_EIN T 5 FLL_LOCK_EINT 4 GP5_EINT 3 GP4_EINT 2 GP3_EINT 1 GP2_EINT 0 GP1_EINT Register 79h Interrupt Status 1 w DEFAULT DESCRIPTION MICBIAS Short ...
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WM8903 REGISTER BIT LABEL ADDRESS R122 (7Ah) 15 IM_MICSHRT_EINT Interrupt Status 1 Mask 14 IM_MICDET_EINT 13 IM_WSEQ_BUSY_EIN T 5 IM_FLL_LOCK_EINT 4 IM_GP5_EINT 3 IM_GP4_EINT 2 IM_GP3_EINT 1 IM_GP2_EINT 0 IM_GP1_EINT Register 7Ah Interrupt Status 1 Mask REGISTER BIT LABEL ADDRESS ...
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Production Data REGISTER BIT LABEL ADDRESS R128 (80h) FLL_GAIN [3:0] 7:4 FLL Control 1 FLL_HOLD 3 2 FLL_FRAC FLL_ENA 0 Register 80h FLL Control 1 w DEFAULT DESCRIPTION Gain applied to error 0000 0000 = x 1 (Recommended value) 0001 ...
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WM8903 REGISTER BIT LABEL ADDRESS R129 (81h) FLL_CLK_SRC 12:11 FLL Control [1:0] 2 10:9 FLL_CLK_REF _DIV [1:0] 8:6 FLL_CTRL_RA TE [2:0] 5:3 FLL_OUTDIV [2:0] FLL_FRATIO 2:0 [2:0] Register 81h FLL Control 2 w DEFAULT DESCRIPTION FLL Clock source 00 00 ...
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Production Data REGISTER BIT LABEL ADDRESS R130 (82h) FLL_K [15:0] 15:0 FLL Control 3 Register 82h FLL Control 3 REGISTER BIT LABEL ADDRESS R131 (83h) 9:0 FLL_N [9:0] FLL Control 4 Register 83h FLL Control 4 REGISTER BIT LABEL ADDRESS ...
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WM8903 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 67 Recommended External Components Notes: 1. Decoupling Capacitors X5R ceramic capacitor is recommended for capacitors C1, C2, C3, C4, C6, C7, C12 and C13. All decoupling capacitors should be positioned as close to ...
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Production Data 3. Zobel Networks The Zobel network shown in Figure 67 is required on HPOUTL, HPOUTR, LINEOUTL and LINEOUTR whenever that output is enabled. Stability of these ground-referenced outputs across all process corners cannot be guaranteed without the Zobel ...
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WM8903 MIC DETECTION SEQUENCE USING MICBIAS CURRENT This section details an example sequence which summarises how the host processor can configure and detect the events supported by the MICBIAS current detect function (see “Electret Condenser Microphone Interface”): • • Figure ...
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Production Data STEP 1 Mic not inserted. To detect mic insertion, Host processor must initialise interrupts and clear MICDET_INV = 0. At every step, the host processor should poll the interrupt status register. Mechanical bounce of jack socket during Mic ...
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WM8903 PACKAGE DIMENSIONS FL: 40 PIN QFN PLASTIC PACKAGE D2 EXPOSED 6 GND PADDLE (A3 SEATING PLANE Dimensions (mm) Symbols MIN NOM A ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...