WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 42

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
ANALOGUE-TO-DIGITAL CONVERTER (ADC)
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Table 9 Digital Microphone Interface Control
Note that, in addition to setting the ADC_DIG_MIC bit as described in Table 9, the pins
GPIO1/DMIC_LR and GPIO2/DMIC_DAT must also be configured to provide the digital microphone
interface function. See “General Purpose Input/Output (GPIO)” for details.
The WM8903 uses two 24-bit, 128x oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. An oversample
rate of 64x can also be supported - see “Clocking and Sample Rates” for details. The ADC full-scale
input level is proportional to AVDD - see “Electrical Characteristics”. Any input signal greater than full
scale may overload the ADC and cause distortion.
The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits.
Table 10 ADC Enable Control
ADC DIGITAL VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to
+17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for
a given eight-bit code is detailed in Table 12.
The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the
ADCL_VOL or ADCR_VOL control data is loaded into the respective control register, but does not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to ADC_VU. This makes it possible to update the gain of both channels simultaneously.
R164 (A4h)
Clock Rate
Test 4
R18 (12h)
Power
Management
6
REGISTER
REGISTER
ADDRESS
ADDRESS
BIT
BIT
9
1
0
ADC_DIG_MIC
ADCL_ENA
ADCR_ENA
LABEL
LABEL
DEFAULT
DEFAULT
0
0
0
Enables Digital Microphone mode.
0 = Audio DSP input is from ADC
1 = Audio DSP input is from digital
microphone interface
Left ADC Enable
0 = disabled
1 = enabled
Right ADC Enable
0 = disabled
1 = enabled
PD, Rev 4.0, September 2010
DESCRIPTION
DESCRIPTION
Production Data
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