WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 92

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
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When the BCLK pin is an output (BCLK_DIR=1), BCLK is derived from the internal CLK_SYS signal
(see “Clocking and Sample Rates”). In this case, the BCLK frequency is controlled in relation to
CLK_SYS by the BCLK_DIV register field. When BCLK is an input, BCLK_DIV has no effect.
When the LRC pin is an output (LRCLK_DIR=1), LRC is derived from BCLK (irrespective of whether
BCLK is an input or output). In this case, the LRC frequency is controlled in relation to BCLK by the
LRCLK_RATE register field. When LRC is an input, LRCLK_RATE has no effect.
BCLK_DIV and LRCLK_RATE are defined in Table 57. The clocking scheme is illustrated in the
“Clocking and Sample Rates” section - see Figure 55.
Table 57 Digital Audio Interface Clock Control
R25 (19h)
Audio
Interface 1
R26 (1Ah)
Audio
Interface 2
R27 (1Bh)
Audio
Interface 3
REGISTER
ADDRESS
10:0
BIT
4:0
9
6
LRCLK_DIR
BCLK_DIR
BCLK_DIV [4:0]
LRCLK_RATE
[10:0]
LABEL
000_0010
DEFAULT
0_1000
_0010
0
0
Audio Interface LRC Direction
0 = LRC is input
1 = LRC is output
Audio Interface BCLK Direction
0 = BCLK is input
1 = BCLK is output
BCLK Frequency (Master Mode)
00000 = CLK_SYS
00001 = Reserved
00010 = CLK_SYS / 2
00011 = CLK_SYS / 3
00100 = CLK_SYS / 4
00101 = CLK_SYS / 5
00110 = Reserved
00111 = CLK_SYS / 6
01000 = CLK_SYS / 8 (default)
01001 = CLK_SYS / 10
01010 = Reserved
01011 = CLK_SYS / 12
01100 = CLK_SYS / 16
01101 = CLK_SYS / 20
01110 = CLK_SYS / 22
01111 = CLK_SYS / 24
10000 = Reserved
10001 = CLK_SYS / 30
10010 = CLK_SYS / 32
10011 = CLK_SYS / 44
10100 = CLK_SYS / 48
LRC Rate (Master Mode)
LRC clock output = BCLK /
LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
50:50 LRCLK duty cycle is only
guaranteed with even values (8, 10,
… 2046).
PD, Rev 4.0, September 2010
DESCRIPTION
Production Data
92