WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 84

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
DIGITAL AUDIO INTERFACE
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The digital audio interface is used for inputting DAC data into the WM8903 and outputting ADC data
from it. The digital audio interface uses four pins:
The clock signals BCLK and LRCLK can be outputs when the WM8903 operates as a master, or
inputs when it is a slave (see “Master And Slave Mode Operation” below).
Note that the BCLK pin can also support other functions, as described under “General Purpose
Input/Output (GPIO)”. BCLK is the default function on this pin (GP5_FN = 1h). Under default
conditions, the other GPIO control fields for this pin have no effect.
Four different audio data formats are supported:
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All four of these modes are MSB first. They are described in “Audio Data Formats (Normal Mode)”
below. Refer to the “Signal Timing Requirements” section for timing information.
Time Division Multiplexing (TDM) is available in all four data format modes. The WM8903 can be
programmed to send and receive data in one of two time slots.
PCM operation is supported using the DSP mode.
MASTER AND SLAVE MODE OPERATION
The WM8903 digital audio interface can operate in master or slave mode, as shown in Figure 36 and
Figure 37.
Figure 36 Master Mode
In master mode, BCLK is derived from CLK_SYS via a programmable division set by BCLK_DIV.
In master mode, LRC is derived from BCLK via a programmable division set by LRCLK_RATE. The
BCLK input to this divider may be internal or external, allowing mixed master and slave modes.
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I2S
DSP mode
ADCDAT: ADC data output
DACDAT: DAC data input
LRC: DAC and ADC data alignment clock
BCLK: Bit clock, for synchronisation
Figure 37 Slave Mode
PD, Rev 4.0, September 2010
Production Data
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