WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 91

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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Table 56 Digital Audio Interface Data Control
Note that the WM8903 is a 24-bit device. In 32-bit mode (AIF_WL=11), the 8 LSBs are ignored on
the receiving side and not driven on the transmitting side.
BCLK AND LRCLK CONTROL
The audio interface can be programmed to operate in master mode or slave mode using the
BCLK_DIR and LRCLK_DIR register bits. In master mode, the BCLK and LRCLK signals are
generated by the WM8903 when any of the ADCs or DACs is enabled. In slave mode, the BCLK and
LRCLK clock outputs are disabled by default to allow another digital audio interface to drive these
pins.
It is also possible to force the BCLK or LRCLK signals to be output using BCLK_DIR and
LRCLK_DIR, allowing mixed master and slave modes. The BCLK_DIR and LRCLK_DIR fields are
defined in Table 57.
When BCLK is not selected (GP5_FN ≠ 1), the WM8903 uses the MCLK input as the Bit Clock,
provided that BCLK_DIR is set to 0 to configure BCLK as an input, ie. BCLK slave mode. This
configuration can offer power consumption benefits in addition to flexibility of GPIO functionality,
R38 (26h)
ADC Digital 0
REGISTER
ADDRESS
BIT
3:2
1:0
7
4
1
0
AIF_BCLK_INV
AIF_LRCLK_INV
AIF_WL [1:0]
AIF_FMT [1:0]
ADCL_DATINV
ADCR_DATINV
LABEL
DEFAULT
00
10
0
0
0
0
BCLK Invert
0 = BCLK not inverted
1 = BCLK inverted
LRC Polarity / DSP Mode A-B
select.
Right, left and I
polarity
0 = Not Inverted
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK
rising edge after LRC rising edge
(mode A)
1 = MSB is available on 1st BCLK
rising edge after LRC rising edge
(mode B)
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Digital Audio Interface Format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = DSP
Left ADC Invert
0 = Left ADC output not inverted
1 = Left ADC output inverted
Right ADC Invert
0 = Right ADC output not inverted
1 = Right ADC output inverted
PD, Rev 4.0, September 2010
DESCRIPTION
2
S modes – LRC
WM8903
91