WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 122

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 (0Ah)
11 (0Bh)
12 (0Ch)
WM8903
w
0 (00h)
1 (01h)
2 (02h)
3 (03h)
4 (04h)
5 (05h)
6 (06h)
7 (07h)
8 (08h)
9 (09h)
WSEQ
INDEX
REGISTER
ADDRESS
R14 (0Eh)
R15 (0Fh)
R65 (41h)
R17 (11h)
R65 (41h)
R17 (11h)
R22 (16h)
R13 (Dh)
R4 (04h)
R5 (05h)
R4 (04h)
R5 (5h)
R5 (5h)
WIDTH
5 bits
2 bits
8 bits
2 bits
2 bits
2 bits
2 bits
2 bits
2 bits
1 bit
1 bit
1 bit
1 bit
Index addresses 0 to 31 may be programmed to users’ own settings at any time, as described in
“Programming a Sequence” Users’ own settings remain in memory and are not affected by software
resets (i.e. writing to Register R0). However, any non-default sequences are lost when the device is
powered down.
START-UP SEQUENCE
The Start-up sequence is initiated by writing 0100h to Register R111 (6Fh). This single operation
starts the Control Write Sequencer at Index Address 0 (00h) and executes the sequence defined in
Table 79.
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately
425ms to run.
START
Bit 0
Bit 1
Bit 0
Bit 1
Bit 0
Bit 0
Bit 3
Bit 1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 1
DATA
1Ah
F7h
01h
03h
00h
00h
00h
01h
01h
03h
03h
03h
01h
DELAY
Bh
0h
9h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
EOS
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
POBCTRL = 1
ISEL [1:0] = 10b
STARTUP_BIAS_ENA = 1
BIAS_ENA = 0
(delay = 0.5625ms)
SPK_DISCHARGE = 1
(delay = 32.5ms)
SPKL_ENA = 1
SPKR_ENA = 1
(delay = 0.5625ms)
SPK_DISCHARGE = 0
(delay = 0.5625ms)
VMID_TIE_ENA = 1
BUFIO_ENA = 1
VMID_IO_ENA = 1
VMID_SOFT = 10
VMID_RES = 11
VMID_BUF_ENA = 1
(delay = 128.5ms)
SPKL_ENA = 0
SPKR_ENA = 0
(delay = 0.5625ms)
VMID_SOFT = 00
(delay = 0.5625ms)
VMID_RES [1:0] = 01b
(delay = 0.5625ms)
BIAS_ENA = 1
(delay = 0.5625ms)
HPL_PGA_ENA = 1
HPR_PGA_ENA = 1
(delay = 0.5625ms)
MIXOUTL = 1
MIXOUTR = 1
(delay = 0.5625ms)
LINEOUTL_PGA_ENA = 1
LINEOUTR_PGA_ENA = 1
(delay = 0.5625ms)
CLK_DSP_ENA = 1
(delay = 0.5625ms)
DESCRIPTION
PD, Rev 4.0, September 2010
Production Data
122