WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 80

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
CHARGE PUMP
w
The WM8903 incorporates a dual-mode Charge Pump which generates the supply rails for the
headphone and line output drivers, HPOUTL, HPOUTR, and LINEOUTL and LINEOUTR. The
Charge Pump has a single supply input, CPVDD, and generates split rails VPOS and VNEG
according to the selected mode of operation. The Charge Pump connections are illustrated in Figure
35 (see the “Electrical Characteristics” section for external component values). An input decoupling
capacitor may also be required at CPVDD, depending upon the system configuration.
Figure 35 Charge Pump External Connections
The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts
the output voltages (VPOS and VNEG) as well as the switching frequency in order to optimise the
power consumption according to the operating conditions. This can take two forms, which are
selected using the CP_DYN_PWR register bit.
Under Register control, the HPOUTL_VOL, HPOUTR_VOL, LINEOUTL_VOL and LINEOUTR_VOL
register settings are used to control the charge pump mode of operation.
Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of
operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised
in real time, but can only be used if the DAC is the only signal source. This mode should not be used
if any of the bypass paths are used to mix analogue inputs into the output signal path.
Under the recommended usage conditions of the WM8903, the Charge Pump will be enabled by
running the default Start-Up sequence as described in the “Control Write Sequencer” section.
(Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user does not
need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register control;
Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.
When digital sidetone is used (see “Digital Mixing”), it is recommended that the Charge Pump
operates in Register Control mode only (CP_DYN_PWR = 0). This is because the Dynamic Control
mode (Class W) does not measure the sidetone signal level and hence the Charge Pump
configuration cannot be optimised for all signal conditions when digital sidetone is enabled; this could
lead to signal clipping.
The MCLK signal must be present for the charge pump to function. The clock division from MCLK is
handled transparently by the WM8903 without user intervention, as long as MCLK and sample rates
are set correctly (see “Clocking and Sample Rates” section). The clock divider ratio depends on the
SAMPLE_RATE [3:0], CLK_SYS_MODE [1:0], and CLK_SYS_RATE [3:0] register settings.
The charge pump requires a minimum CLK_SYS frequency of 2.8224MHz.
•
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Register control (CP_DYN_PWR = 0)
Dynamic control (CP_DYN_PWR = 1)
PD, Rev 4.0, September 2010
Production Data
80