WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 56

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
DIGITAL-TO-ANALOGUE CONVERTER (DAC)
w
The digital sidetone volume settings are shown in Table 28.
Table 28 Digital Sidetone Volume
The WM8903 DACs receive digital input data from the DACDAT pin and via the digital sidetone path
(see “Digital Mixing” section). The digital audio data is converted to oversampled bit streams in the
on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta
DACs, which convert them to high quality analogue audio signals. The Wolfson SmartDAC™
architecture offers reduced power consumption, whilst also delivering a reduction in high frequency
noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high
linearity and low distortion.
The analogue outputs from the DACs can then be mixed with other analogue inputs before being
sent to the analogue output pins (see “Output Signal Path”).
The DACs are enabled by the DACL_ENA and DACR_ENA register bits.
Table 29 DAC Enable Control
DAC DIGITAL VOLUME CONTROL
The output level of each DAC can be controlled digitally over a range from -71.625dB to 0dB in
0.375dB steps. The level of attenuation for an eight-bit code is detailed in Table 31.
The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the
DACL_VOL or DACR_VOL control data is loaded into the respective control register, but does not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to DAC_VU. This makes it possible to update the gain of both channels simultaneously.
R18 (12h)
Power
Management
6
REGISTER
ADDRESS
ADCR_DAC_SVOL
ADCL_DAC_SVOL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BIT
OR
3
2
DACL_ENA
DACR_ENA
LABEL
DEFAULT
0
0
SIDETONE VOLUME
Left DAC Enable
0 = DAC disabled
1 = DAC enabled
Right DAC Enable
0 = DAC disabled
1 = DAC enabled
-36
-33
-30
-27
-24
-21
-18
-15
-12
-9
-6
-3
0
0
0
0
PD, Rev 4.0, September 2010
DESCRIPTION
Production Data
56