WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 67

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
Table 41 Headphone / Line Output Pop Suppression Control
R94 (5Eh)
Analogue
Lineout 0
REGISTER
ADDRESS
BIT
7
6
5
4
3
2
1
0
LINEOUTL_RMV
_SHORT
LINEOUTL_ENA_
OUTP
LINEOUTL_ENA_
DLY
LINEOUTL_ENA
LINEOUTR_RMV
_SHORT
LINEOUTR_ENA
_OUTP
LINEOUTR_ENA
_DLY
LINEOUTR_ENA
LABEL
DEFAULT
0
0
0
0
0
0
0
0
Removes LINEOUTL short
0 = LINEOUTL short enabled
1 = LINEOUTL short removed
For normal operation, this bit should
be set as the final step of the
LINEOUTL Enable sequence.
Enables LINEOUTL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
Enables LINEOUTL intermediate
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTL_ENA.
Enables LINEOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTL Enable sequence.
Removes LINEOUTR short
0 = LINEOUTR short enabled
1 = LINEOUTR short removed
For normal operation, this bit should
be set as the final step of the
LINEOUTR Enable sequence.
Enables LINEOUTR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
Enables LINEOUTR intermediate
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTR_ENA.
Enables LINEOUTR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTR Enable sequence.
PD, Rev 4.0, September 2010
DESCRIPTION
WM8903
67