WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 66
WM8903LGEFK/RV
Manufacturer Part Number
WM8903LGEFK/RV
Description
Audio CODECs ULTRA LOW PWR HI FI CODEC
Manufacturer
Wolfson Microelectronics
Specifications of WM8903LGEFK/RV
Audio Codec Type
Stereo Codec
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
6
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Sampling Rate
96kHz
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Adcs / Dacs Signal To Noise Ratio
96dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Quantity
Price
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Manufacturer:
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WM8903
w
REGISTER
ADDRESS
BIT
5
4
3
2
1
0
HPL_ENA_DLY
HPL_ENA
HPR_RMV_SHO
RT
HPR_ENA_OUTP
HPR_ENA_DLY
HPR_ENA
LABEL
DEFAULT
0
0
0
0
0
0
Enables HPL intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPL_ENA.
Enables HPL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPL
Enable sequence.
Removes HPR short
0 = HPR short enabled
1 = HPR short removed
For normal operation, this bit should
be set as the final step of the HPR
Enable sequence.
Enables HPR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
Enables HPR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPR_ENA.
Enables HPR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the HPR
Enable sequence.
PD, Rev 4.0, September 2010
DESCRIPTION
Production Data
66