WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 100

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
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USB CLOCKING MODE
The clock division ratios with CLK_SYS_MODE = 01 or CLK_SYS_MODE = 10 allow compatibility
with a 12MHz USB clock, at sample rates up to 48kHz. For example, with a 12MHz (USB) clock and
8kHz sample rate, the CLK_SYS to fs ratio is 1500. In this case, the required setting for
CLK_SYS_RATE is 1001.
Note that 44.1kHz and related sample rates are approximate when derived from a USB clock. For
example, with a 12MHz MCLK and a division ratio of 272, the exact sample rate obtained is
44.118kHz rather than 44.1kHz. This 0.04% offset is inaudible and can be ignored. 48kHz and
related sample rates are exact in all modes of operation, provided that MCLK itself is exact.
ADC / DAC OPERATION AT 88.2K / 96K
The WM8903 supports ADC or DAC operation at 88.2kHz and 96kHz sample rates. This section
details specific conditions applicable to these operating modes. Note that simultaneous ADC and
DAC operation at 88.2kHz or 96kHz is not possible.
For DAC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are
detailed in Table 64.
Note that, for DAC operation at 88.2kHz or 96kHz sample rates, the ADCs must both be disabled
(ADCL_ENA = 0 and ADCR_ENA = 0). Also, the DAC_OSR register should be set to 0.
The CLK_SYS frequency is derived from MCLK. Note that the maximum MCLK frequency is defined
in the “Signal Timing Requirements” section.
Table 64 DAC Operation at 88.2kHz and 96kHz Sample Rates
For ADC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are
detailed in Table 65.
Note that ADC operation at these sample rates is achieved by setting the SAMPLE_RATE field to
half the required sample rate (eg. select 48kHz for 96kHz mode). In these modes, the BCLK_DIV
field is set to select BCLK at double the normal rate.
Note that, for ADC operation at 88.2kHz or 96kHz sample rates, the DACs must both be disabled
(DACL_ENA = 0 and DACR_ENA = 0).
The CLK_SYS frequency is derived from MCLK. Note that the maximum MCLK frequency is defined
in the “Signal Timing Requirements” section.
Table 65 ADC Operation at 88.2kHz and 96kHz Sample Rates
SAMPLE RATE
SAMPLE RATE
88.2kHz
88.2kHz
96kHz
96kHz
SAMPLE_RATE = 1001
CLK_SYS_RATE = 0001
SAMPLE_RATE = 1010
CLK_SYS_RATE = 0001
SAMPLE_RATE = 0111
CLK_SYS_RATE = 0001
CLK_SYS_MODE = 00
SAMPLE_RATE = 1000
CLK_SYS_RATE = 0001
CLK_SYS_MODE = 00
REGISTER CONFIGURATION
REGISTER CONFIGURATION
CLK_SYS_MODE = 00
CLK_SYS_MODE = 01
CLK_SYS_MODE = 10
CLK_SYS_MODE = 00
CLK_SYS_MODE = 10
BCLK_DIV = 00010
LRCLK_RATE = 040h
BCLK_DIV = 00010
LRCLK_RATE = 040h
PD, Rev 4.0, September 2010
CLK_SYS / fs RATIO
CLK_SYS / fs RATIO
128 x fs
136 x fs
125 x fs
128 x fs
125 x fs
128 x fs
128 x fs
Production Data
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