MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet - Page 12

• Manufacturer Part Number: MT48LC2M32B2TG-6:G
• Description: DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2TG-6:G

• Density: 64 Mb
• Maximum Clock Rate: 166 MHz
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 2Mx32
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Register Definition
Mode Register
Burst Length
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CL, an operating mode
and a write burst mode, as shown in Figure 4 on page 13. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CL, M7, and M8 specify the operating
mode, M9 specifies the write burst mode, and M10 is reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 4. The burst length determines the maximum
number of column locations that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available for the sequential type. The full-
page burst is used in conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A7 when the
BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within the page if the boundary is
reached.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM