MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet - Page 25

• Manufacturer Part Number: MT48LC2M32B2TG-6:G
• Description: DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2TG-6:G

• Density: 64 Mb
• Maximum Clock Rate: 166 MHz
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 2Mx32
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Figure 12:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
READ-to-WRITE
Note:
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 12 and in Figure 13
on page 26. The DQM signal must be asserted (HIGH) at least two clocks prior to the
WRITE command (DQM latency is two clocks for output buffers) to suppress data-out
from the READ. After the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal; provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 in Figure 13, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6
would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 12
shows the case where the clock frequency allows for bus contention to be avoided
without adding an NOP cycle, and Figure 13 shows the case where the additional NOP is
needed.
COMMAND
ADDRESS
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
DQM
CLK
DQ
T0
BANK,
COL n
READ
T1
NOP
25
T2
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
D
t HZ
OUT
t CK
n
DON’T CARE
T4
BANK,
COL b
WRITE
D
IN
b
t
DS
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands