MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet - Page 30

• Manufacturer Part Number: MT48LC2M32B2TG-6:G
• Description: DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2TG-6:G

• Density: 64 Mb
• Maximum Clock Rate: 166 MHz
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 2Mx32
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Figure 17:
Figure 18:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
WRITE Burst
WRITE-to-WRITE
Note:
COMMAND
COMMAND
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and writes will
not be executed. An example is shown in Figure 20 on page 31. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued
which the last desired input data element is registered. The “two-clock” write-back
requires at least one clock plus time, regardless of frequency, in auto precharge mode. In
addition, when truncating a WRITE burst, the DQM signal must be used to mask input
data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE
command. An example is shown in Figure 21 on page 32. Data n + 1 is either the last of a
burst of two or the last desired of a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
precharge will actually begin coincident with the clock-edge (T2 in Figure 21) on a “one-
clock”
(between T2 and T3 in Figure 21).
ADDRESS
ADDRESS
TRANSITIONING DATA
DQM is LOW. Each WRITE command may be to any bank.
CLK
CLK
DQ
DQ
t
WR and sometime between the first and second clock on a “two-clock”
WRITE
WRITE
BANK,
COL n
BANK,
COL n
D
T0
T0
D
n
IN
n
IN
n + 1
NOP
NOP
n + 1
T1
T1
D
D
IN
IN
DON’T CARE
30
WRITE
BANK,
COL b
NOP
T2
T2
D
b
IN
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
t
WR after the clock edge at
©2001 Micron Technology, Inc. All rights reserved.
t
64Mb: x32 SDRAM
RP is met. The
Commands
t
WR