MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet - Page 14

• Manufacturer Part Number: MT48LC2M32B2TG-6:G
• Description: DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2TG-6:G

• Density: 64 Mb
• Maximum Clock Rate: 166 MHz
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 2Mx32
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Table 5:
CAS Latency
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Burst Definition
Notes:
1. For BL = 2, A1–A7 select the block-of-two burst; A0 selects the starting column within the
2. For BL = 4, A2–A7 select the block-of-four burst; A0–A1 select the starting column within
3. For BL = 8, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within
4. For a full-page burst, the full row is selected and A0–A7 select the starting column.
5. Whenever a boundary of the block is reached within a given sequence above, the following
6. For BL = 1, A0–A7 select the unique column to be accessed, and mode register bit M3 is
The CAS latency is the delay, in clock cycles, between the registration of a READ
command and the availability of the first piece of output data. The latency can be set to
1, 2, or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to 2 clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 5 on page 15. Table 6 on page 15 indicates the
operating frequencies at which each CAS latency setting can be used.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
Full page
block.
the block.
the block.
access wraps within the block.
ignored.
Length
Burst
(256)
2
4
8
Starting Column Address
A2
0
0
0
0
1
1
1
1
(location 0–256)
n = A0–A10
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
14
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Type = Sequential
Cn, Cn + 1, Cn + 2,
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
…Cn - 1, Cn…
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
Functional Description
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0