MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet - Page 39

• Manufacturer Part Number: MT48LC2M32B2TG-6:G
• Description: DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2TG-6:G

• Density: 64 Mb
• Maximum Clock Rate: 166 MHz
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 2Mx32
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Table 9:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Current State
Row active
precharge
precharge
disabled)
disabled)
Write
(auto
(auto
Read
Any
Idle
Truth Table 3 – Current State Bank n, Command to Bank n
Notes 1–6 apply to entire table; notes appear below and on next page
Notes:
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table is bank-specific, except where noted; that is, the current state is for a specific
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
after
bank and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
Idle:
Row active: A row in the bank has been activated, and
Read:
Write:
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 9 and according to Table 10 on page 41.
Precharging:
Row activating:
Read with auto
precharge enabled:
Write w/auto
precharge enabled:
t
CAS#
XSR has been met (if the previous state was self refresh).
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
The bank has been precharged, and
accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminated.
WE#
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
Starts with registration of a PRECHARGE command and ends when
t
Starts with registration of an ACTIVE command and ends when
is met. After
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
RP is met. After
n - 1
39
was HIGH and CKE
t
RCD is met, the bank will be in the row active state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
Command (Action)
t
t
RP has been met. After
RP has been met. After
t
RP has been met.
n
is HIGH (see Table 8 on page 38) and
t
RCD has been met. No data bursts/
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
t
t
RP is met, the bank
RP is met, the bank
Commands
Notes
11
10
10
10
10
10
10
7
7
8
8
9
8
9
t
RCD