MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet - Page 32

• Manufacturer Part Number: MT48LC2M32B2TG-6:G
• Description: DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC2M32B2TG-6:G

• Density: 64 Mb
• Maximum Clock Rate: 166 MHz
• Package: 86TSOP-II
• Address Bus Width: 13 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 17|7.5|5.5 ns
• Operating Temperature: 0 to 70 °C
• Organization: 2Mx32
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

Figure 21:
PRECHARGE
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
WRITE-to-PRECHARGE
Note:
COMMAND
COMMAND
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 22 on page 33, where data n is
the last desired data element of a longer burst.
The PRECHARGE command (Figure 23 on page 34) is used to deactivate the open row in
a particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0 and BA1 select the bank. When all
banks are to be precharged, inputs BA0 and BA1 are treated as “Don’t Care.” Aftera bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank.
t
t
WR = 1 CLK (
WR = 2 CLK (when
ADDRESS
ADDRESS
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
DQM
DQM
CLK
DQ
DQ
t
CK >
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
t
t
WR)
WR >
t
n + 1
n + 1
NOP
CK)
NOP
T1
D
D
IN
IN
t
WR
32
PRECHARGE
(a or all)
BANK
NOP
T2
t
WR
PRECHARGE
(a or all)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
BANK
RP) after the PRECHARGE command is issued.
T3
NOP
t RP
NOP
NOP
T4
t RP
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
BANK a,
ACTIVE
ROW
NOP
T6
Commands