M54455EVB Freescale, M54455EVB Datasheet - Page 10

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

are set on the CPLD mode signals (CPLD_MODE[1:0]). The CPLD_MODE signals are set by the CPLD
configuration switch, SW1. See
and their corresponding boot mode configurations.
4.3.1
If the BOOTMOD pins are 00 during reset, the MCF5445x RCON register determines the chip
configuration after reset, regardless of the states of the external data pins. The RCON register specifies the
following default configuration for the MCF54455:
4.3.2
If the BOOTMOD pins are 10 during reset, the MCF5445x configuration after reset is determined
according to the levels driven onto the FB_AD[7:0] pins. On the M54455EVB, the FB_AD[7:0] pins are
actively driven by an 8-bit buffer enabled when the MCF5445x RSTOUT signal is asserted. The values
driven by the buffer are set by the SW3 DIP switch settings. Refer to
information.
10
•
•
•
•
•
BOOTMOD[1:0]
PCI enabled, muxed Flexbus address/data, 8-bit port-size boot
PLL enabled
PCI host mode
66MHz PCI slew rate mode
PLL multiplier: f
00
01
10
11
Default Configuration (SW1[2:1] = ON:ON)
Parallel Configuration (SW1[2:1] = OFF:ON)
SW1[2:1]
OFF:OFF
ON:OFF
OFF:ON
VCO
ON:ON
= 6 × f
Table 3. M54455EVB Boot Mode Selection
Section 4.14,
REF
Boot from Flexbus with defaults (from RCON register)
Reserved
Boot from Flexbus and override defaults via data bus (FB_AD[7:0])
Boot from Flexbus and override defaults via serial boot facility (SPI memory)
M54455EVB User’s Manual, Rev. 4
“CPLD” for more details.
Meaning
Table 4
Table 3
for the configuration setting
shows the SW1 settings
Freescale Semiconductor