M54455EVB Freescale, M54455EVB Datasheet - Page 31

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.14.3.2
Following reset, PHY0_PWRDN, ATA_ENABLE, and ULPI_RESET pins are set according to the
CPLD_MODE switch (SW1) settings. The CPLD_CONTROL register allows you to override these
switch settings.
4.14.3.3
CPLD_SDODT controls the DDR SDRAM on-die termination pins.
Freescale Semiconductor
FEC0
Field
Field
ULPI
ODT
7–3
ATA
7–2
1–0
2
1
0
Address: 0x0800_0001 (CPLD_CONTROL)
Address: 0x0800_0002 (CPLD_SDODT)
Reset:
Reset:
FEC0 PHY mode
0 FEC0 Ethernet PHY in normal/functional mode
1 FEC0 Ethernet PHY in power down mode
Reserved, must be cleared.
ATA and FEC1 PHY mode
0 Full ATA data bus enabled/FEC1 PHY in power down mode
1 Upper 8-bits of ATA data bus disabled; FEC1 PHY in normal/functional mode
ULPI PHY mode
0 ULPI PHY in normal/functional mode
1 ULPI PHY held in reset state
W
W
Reserved, must be cleared.
Control state of the corresponding DDR SDRAM on-die termination pins. These pins are for test purposes only. The
M54455EVB provides external parallel termination for the DDR2 interface.
R
R
CPLD Control Register (CPLD_CONTROL)
CPLD On-Die Termination Register (CPLD_SDODT)
0
0
0
0
7
7
6
0
0
6
0
0
Table 29. CPLD_CONTROL Field Descriptions
Table 30. CPLD_SDODT Field Descriptions
Figure 20. CPLD_CONTROL Register
Figure 21. CPLD_SDODT Register
M54455EVB User’s Manual, Rev. 4
0
0
0
0
5
5
Description
0
0
0
0
4
4
Description
0
0
0
0
3
3
FEC0
—
0
0
2
2
ATA
—
0
1
1
ODT
ULPI
—
0
0
0
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