M54455EVB Freescale, M54455EVB Datasheet - Page 28

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.14.1.3
The ULPI PHY’s RESET signal is connected to the ULPI_RESET output from the CPLD. When this
signal is asserted, the PHY is held in its reset state. When using the on-chip FS/LS transceiver USB
interface, this switch should be ON. Refer to
4.14.1.4
The upper eight bits of the ATA data bus are multiplexed with the FEC1 RMII interface. To use the full
ATA interface, the FEC1 interface must be disabled. The MCF5445x provides pin assignment control to
route the proper integrated peripheral signals to the external pins. The M54455EVB provides this switch
and a programmable bit in the CPLD_CONTROL register to select the appropriate board level routing.
The upper half of the ATA level-shifting buffer is controlled by the CPLD output signal ATA_ENABLE.
When this signal is asserted, the multiplexed ATA/FEC1 signals from the MCF5445x is enabled to/from
the 40-pin ATA connector.
The FEC1 port of the dual-port 10/100-Mbps Ethernet PHY is powered down when the PHY1_PWRDN
signal is asserted by the CPLD.
The ATA_DATA11 pin is multiplexed with the FEC1_RMII_REF_CLK clock. This clock is generated by
the CY22393 clock generator and driven through a buffer controlled by the CPLD’s RMIICLK2_EN
signal. When the ATA_ENABLE signal is asserted, the RMIICLK2_EN signal is deasserted, shutting off
the clock and allowing this signal to be used as ATA_DATA11.
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ULPI PHY Reset Control
ATA/FEC1 Selection
The ULPI PHY still drives CLKOUT even when it is held in reset.
SW1 [3]
OFF
ON
Table 22. Flash Chip Select Configuration
SW1 [4]
OFF
ON
Table 23. ULPI PHY Reset Control
M54455EVB User’s Manual, Rev. 4
Flash1 is the boot device
Flash0 is the boot device
FLASH1_CS = FB_CS0
FLASH0_CS = FB_CS1
FLASH1_CS = FB_CS1
FLASH0_CS = FB_CS0
ULPI chip not held in reset state
(ULPI_RESET deasserted/driven low)
ULPI chip held in reset state
(ULPI_RESET asserted/driven high)
Meaning
Section 4.10,
NOTE
Meaning
“USB” for more details.
Boot custom image
Application
Boot U-Boot
Freescale Semiconductor