M54455EVB Freescale, M54455EVB Datasheet - Page 29

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.14.1.5
The FEC0 port of the dual-port 10/100-Mbps Ethernet PHY can be powered down by the CPLD’s
PHY0_PWRDN signal. The default state of this signal is determined by SW1[6], but it can be overridden
by the CPU via the CPLD_CONTROL register.
4.14.1.6
The MCF5445x test mode enable (active high) signal state is controlled by the CPLD’s TEST signal. The
state of this signal is determined by SW1[8].
4.14.2
Optionally populated resistors on the M54455EVB allow the revision to be indicated at the time of
assembly. These resistors connections input to the CPLD, and the values can be read from
CPLD_VERSION register. Refer to the description of the CPLD registers below.
Freescale Semiconductor
M54455EVB Revision
FEC0 PHY Power Down
MCF5445x Test Mode
SW1 [5]
Test mode is for Freescale test purposes only. Enabling test mode places the
MCF5445x into a non-functional state.
OFF
ON
SW1 [8]
• Full ATA bus enabled (ATA_ENABLE asserted/driven low)
• PHY1 powered down (PHY1_PWRDN asserted/driven low)
• RMIICLK2 is disabled (RMIICLK2_EN deasserted/driven low)
• Upper 8 bits of the ATA data bus disabled (ATA_ENABLE deasserted/driven high)
• PHY1 active (PHY1_PWRDN deasserted/driven high)
• RMIICLK2 is enabled (RMIICLK2_EN asserted/driven high)
OFF
SW1 [6]
ON
OFF
ON
MCF5445x in normal function mode
MCF5445x in factory test mode
Note: This setting is for Freescale use only and places the
PHY0 active (PHY0_PWRDN deasserted/driven high)
PHY0 powered down (PHY0_PWRDN asserted/driven low)
MCF5445x into a non-functional mode.
Table 25. FEC0 PHY Power Down
Table 26. MCF5445x Test Mode
M54455EVB User’s Manual, Rev. 4
Table 24. ATA/FEC1 Selection
NOTE
Meaning
Meaning
Meaning
29