M54455EVB Freescale, M54455EVB Datasheet - Page 21

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.10
The MCF5445x integrates a USB 2.0 dual-role module with the following features:
The M54455EVB provides two interfaces to the single MCF5445x USB controller. Only one of these
interfaces can be used at any one time.
4.10.1
The on-chip FS/LS transceiver signals are brought out to a type-A USB connector and are intended to be
used for USB host applications. 15-kΩ pull-down and 33-Ω series resistors are provided on the D+ and D-
data signals. Power to the connector is provided by an external dual-channel power distribution switch
(MIC2026-1YM, U928). The B-channel of this device supplies the power for the type-A connector and is
controlled by the MCF5445x USB_VBUS_EN output control signal.
When the on-chip FS/LS transceiver is used, the ULPI PHY can be put into its reset state. Refer to
Section 4.14,
4.10.2
The ULPI interface of the MCF5445x is also featured on the M54455EVB. An external ULPI physical
layer device, the SMSC USB3300 (U927), connects directly to the MCF5445x ULPI interface. The USB
signals from the ULPI PHY are brought out to a mini-AB USB connector. The ID pin on the mini-AB
connector connects to the ULPI PHY’s ID pin and indicates whether a host or device is connected. The
ULPI PHY has an enable signal connected to the A-channel of the MIC2026 power distribution switch that
is used to supply VBUS when operating as a host.
The RESET signal input to the ULPI PHY is controlled by the system’s CPLD. Refer to
“CPLD” for details.
4.11
The MCF5445x processor features two Fast Ethernet controllers (FEC) with MII and RMII interface
options. The M54455EVB provides a dual 10/100 Mbps Ethernet PHY to interface with the processor’s
FECs. The PHY operates in dual RMII mode. The board also provides two RJ45 connectors with
integrated magnetics and LEDs.
The dual-port 10/100 Mbps provides a power-down feature for each port. You can control these power
down signals via the system’s CPLD.
Freescale Semiconductor
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Support for host and device modes
Support for full speed (FS) and low speed (LS) via an on-chip FS/LS transceiver
Optional UTMI+ Low Pin Count Interface (ULPI) to support high speed (HS) transfers as well as
FS and LS
Uses 60 MHz reference clock based off of the system clock or from an external pin
USB
Ethernet
On-Chip FS/LS Transceiver
ULPI PHY
“CPLD” for details.
M54455EVB User’s Manual, Rev. 4
Section 4.14,
21