M54455EVB Freescale, M54455EVB Datasheet - Page 20

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.9
The primary debug port on the MCF5445x is referred to as the background debug module or BDM. The
standard 26-pin BDM header (J24) is provided on the M54455EVB for attachment of an external BDM
control interface. However, the M54455EVB also features a built-in P&E USB ColdFire Multilink. This
interface is brought out to the I/O back panel to a standard Type-B USB receptacle. Refer to
“I/O Back
USB cable (provided in the M54455EVB kit).
The MCF5445x also features IEEE 1149.1 Test Access Port (JTAG) test logic that can be used for
boundary-scan testability. The access pins for JTAG are multiplexed over the BDM control signals and are
available on J24.
The JTAG_EN input signal to the MCF5445x determines the debug mode: BDM or JTAG. This signal is
controllable by JP903 as shown below.
The TCLK and PSTCLK signals are the only two multiplexed signals that switch input/output state
depending on which debug mode is selected. In BDM mode, the PSTCLK is an output from the MCF5445x
to the external BDM control interface. In JTAG mode, TCLK is the test clock input. The standard 26-pin
BDM header defines pin 24 as PSTCLK. A common practice is to place TCLK on pin 6 of this header.
JP904 is available to control the routing of the multiplexed TCLK_PSTCLK signal to the 26-pin debug
header (J24) as shown below.
20
BDM and JTAG
Panel” for the location of the connector. This allows for run-control debugging with a standard
1
2
This setting is required if an external BDM control interface is
used. If the on-board USB Multilink is used, this jumper setting
is ignored.
This pin was previously specified by Freescale as Developer
Reserved. External BDM control cables may be able to make
use of this pin for JTAG instructions. There is a 10-kΩ
pull-down resistor on the TCK_PSTCLK signal when this
setting is selected.
JP904 Setting
Shunt on 1-2
Shunt on 2-3
Table 11. TCLK/PSTCLK Routing Control
Table 10. Debug Mode Selection
M54455EVB User’s Manual, Rev. 4
JP903 Setting
Shunt on 1-2
Shunt on 2-3
TCLK/PSTCLK on J24[24]
TCLK/PSTCLK on J24[6]
TCLK_PSTCLK Routing
Debug Mode
JTAG
BDM
2
1
Freescale Semiconductor
Section 2.4,