M54455EVB Freescale, M54455EVB Datasheet - Page 26

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M54455EVB

Manufacturer Part Number
M54455EVB
Description
Manufacturer
Freescale
Datasheet

Specifications of M54455EVB

Architecture
32-bit (not ARM)
Lead Free Status / RoHS Status
Supplier Unconfirmed
4.13.1.6
4.13.1.7
4.14
A Xilinx XC95144XL CPLD performs a number of tasks on the M54455EVB including:
26
Address: 0x0900_0018 (FPGA_LEDS)
LED2
LED1
Field
Field
31–8
31–2
LED
7–0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address: 0x0900_0014 (FPGA_7SEGMENT)
1
0
Reset control
Boot mode selection
Peripheral multiplexing and enable/disable control
LED control
Board revision determination
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CPLD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved, must be cleared.
Indicates the hex number you want to display on the 7-segment LED display (U28 on the EVB).
Reserved, must be cleared.
Controls the state of FPGA_LED2. FPGA_LED2 is reference designator D956.
0 Off
1 On
Controls the state of FPGA_LED1. FPGA_LED1 is reference designator D957.
0 Off
1 On
FPGA Seven Segment Display Register (FPGA_7SEGMENT)
FPGA LED Control Register (FPGA_LEDS)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Table 18. FPGA_7SEGMENT Field Descriptions
Table 19. FPGA_LEDS Field Descriptions
Figure 17. FPGA_7SEGMENT Register
Figure 18. FPGA LEDS Register
M54455EVB User’s Manual, Rev. 4
Description
Description
8
7
8
6
7
5
6
Freescale Semiconductor
4
5
3
4
LED
2
3
LED2 LED1
2
0
1
1
0
0
0