M54455EVB Freescale, M54455EVB Datasheet - Page 12

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.3.3
If the BOOTMOD pins are 11 during reset, then the chip configuration after reset is determined by data
obtained from an external SPI memory through serial boot using the SBF_DI, SBF_DO, SBF_CS, and
SBF_CK signals. The internal configuration signals are driven to reflect the data being received from the
external SPI memory to allow for module configuration. See “Serial Boot Facility” and “Chip
Configuration Module” chapters of the MCF54455 Reference Manual for more details.
4.4
A single Cypress CY22393 device generates all of the clock signals on the M54455EVB. Alternatively,
you can supply the clock signals using external SMA connectors for test purposes. The different clock
signals and configurations are described below. Please refer to the MCF54455 Reference Manual for
further information on the clocking requirements for the MCF5445x family.
The CY22393 is programmed prior to assembly on the M54455EVB PCB. There is an I
this device that allows it to be reprogrammed. However, these settings are not retained following a
power-on reset.
The state of the CY22393’s S2 frequency control input pin is controlled by a jumper (H4[3:4]) and the
system FPGA signal, CLK_GEN_S2. The FPGA uses two conditions to determine how to drive the
CLK_GEN_S2 signal: the M66EN signal and a programmable bit in the PCICLKCFG register. The
M66EN signal is a PCI bus signal that is tied to logic 0 if a 33MHz PCI card is installed in any one of the
four PCI slots. By default, the PCICLKCFG[CLKGENS2EN] bit is cleared, which forces the clocks to
33 MHz.
12
Table 5
System Clocks
1
Serial Configuration (SW1[2:1] = OFF:OFF)
This setting is required if booting from Flash device, Flash0, or Flash1.
Pin(s) Affected
(none)
summarizes the three controls over the state of the S2 pin.
Table 4. MCF54455 Parallel Configuration During Reset (continued)
Corresponding SW3
SW3[2]
OFF
OFF
ON
ON
Settings
M54455EVB User’s Manual, Rev. 4
SW3[1]
OFF
OFF
ON
ON
f
e.g. CPU = 266 MHz; PCI = 66 MHz
f
e.g. CPU = 266 MHz; PCI = 33 MHz
f
e.g. CPU = 200 MHz; PCI = 66 MHz
f
e.g. CPU = 200 MHz; PCI = 33 MHz
VCO
VCO
VCO
VCO
= 8 x f
= 16 x f
= 6 x f
= 12 x f
PLL Multiplier (when in a PCI mode)
REF
REF
REF
REF
Function
Freescale Semiconductor
2
C interface on