UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 14

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
UJA1065_7
Product data sheet
6.4.3 Watchdog time-out behavior
6.4.4 Watchdog OFF behavior
The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler.
The period can be changed within any valid trigger window. Whenever the watchdog is
triggered within the window time, the timer will be reset to start a new period.
The watchdog window is defined to be between 50 % and 100 % of the nominal
programmed watchdog period. Any too early or too late watchdog access or wrong Mode
register code access will result in an immediate system reset, entering Start-up mode.
Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the
active watchdog operates in Time-out mode. The watchdog has to be triggered within the
actual programmed period time; see
cyclic wake-up events to the host microcontroller from Standby and Sleep modes.
In Standby and in Flash mode the nominal periods can be changed with any SPI access to
the Mode register.
Any illegal watchdog trigger code results in an immediate system reset, entering Start-up
mode.
The watchdog can be switched off completely in Standby and Sleep modes. For fail-safe
reasons this is only possible if the microcontroller has stopped program execution. To
ensure that there is no program execution, the V1 supply current is monitored by the SBC
while the watchdog is switched off.
When selecting the watchdog OFF code, the watchdog remains active until the
microcontroller supply current has dropped below the current monitoring threshold I
After the supply current has dropped below the threshold, the watchdog stops at the end
of the watchdog period. In case the supply current does not drop below the monitoring
threshold, the watchdog stays active.
Fig 5.
(with different duration if
trigger
via SPI
trigger restarts period
Watchdog triggering using Time-out mode
possible
earliest
trigger
point
desired)
Rev. 07 — 25 February 2010
trigger range
period
Figure
High-speed CAN/LIN fail-safe system basis chip
5. The Time-out mode can be used to provide
trigger range
new period
possible
trigger
latest
point
time-out
UJA1065
© NXP B.V. 2010. All rights reserved.
time-out
mce627
thL(V1)
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