UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 28

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
UJA1065_7
Product data sheet
Fig 15. SPI timing protocol
SDO
SCS
SCK
SDI
6.13 SPI interface
floating
X
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave and multi-master operation. The SPI is configured
for full duplex data transfer, so status information is returned when new control data is
shifted in. The interface also offers a read-only access option, allowing registers to be
read back by the application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge; see
X
•
•
•
•
sampled
SCS - SPI chip select; active LOW
SCK - SPI clock; default level is LOW due to low-power concept
SDI - SPI data input
SDO - SPI data output; floating when pin SCS is HIGH
01
MSB
MSB
Figure
02
15.
14
14
Rev. 07 — 25 February 2010
03
13
13
04
High-speed CAN/LIN fail-safe system basis chip
12
12
15
01
01
16
LSB
LSB
UJA1065
© NXP B.V. 2010. All rights reserved.
floating
mce634
X
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