UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 30

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 5.
[1]
[2]
UJA1065_7
Product data sheet
Bit
15 and 14
13
12
11 to 6
5 to 3
2
1
0
Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,
while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up
mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source
information, confirming the Flash entry sequence. By using the Initializing Flash mode (within t
now successfully enter Flash mode.
See
Section
Mode register bit description (bits 15 to 12 and 5 to 0)
Symbol
A1, A0
RRS
RO
NWP[5:0]
OM[2:0]
SDM
EN
-
6.13.3 Mode register
6.14.1.
In the Mode register the watchdog is defined and re-triggered, and the SBC operating
mode is selected. The Mode register also contains the global enable output bit (EN) and
the Software Development Mode (SDM) control bit. During system operation cyclic
access to the Mode register is required to serve the watchdog. This register can be written
to in all modes.
At system start-up the Mode register must be written to within t
RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and
system mode coding. If an illegal code is detected, access is ignored by the SBC and a
system reset is forced in accordance with the state diagram of the system controller; see
Figure
Description
register address
Read Register
Select
Read Only
see
Operating Mode
Software
Development
Mode
Enable
reserved
Table 6
3.
001
Value
00
1
0
1
0
010
011
100
101
110
111
1
0
1
0
0
Rev. 07 — 25 February 2010
Function
select Mode register
read System Diagnosis register
read System Status register
read selected register without writing to Mode register
read selected register and write to Mode register
Normal mode
Standby mode
initialize Flash mode
Sleep mode
initialize Normal mode
leave Flash mode
Flash mode
Software development mode enabled
normal watchdog, interrupt, reset monitoring and fail-safe
behavior
EN output pin HIGH
EN output pin LOW
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
High-speed CAN/LIN fail-safe system basis chip
[1]
[1]
WD(init)
after system reset) the SBC will
WD(init)
[2]
from releasing
UJA1065
© NXP B.V. 2010. All rights reserved.
30 of 76