UJA1065 NXP Semiconductors, UJA1065 Datasheet - Page 40

• Manufacturer Part Number: UJA1065
• Manufacturer: NXP Semiconductors

Specifications of UJA1065

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
[3]
Table 13.
[1]
[2]
UJA1065_7
Product data sheet
Bit
15 and 14
13
12
11 and 10
9
8
7
6 and 5
4 and 3
2 to 0
In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is
automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing
the LTC bit under software control.
See
Not supported in the UJA1065TW/3V3 version.
Section
Special Mode register and Special Mode Feedback register bit description
Symbol
A1, A0
RRS
RO
-
ISDM
ERREM
-
WDPRE [1:0]
V1RTHC [1:0] V1 Reset Threshold
-
6.13.10 Special Mode register and Special Mode Feedback register
6.14.1.
These registers allow configuration of global SBC parameters during start-up of a system
and allow the settings to be read back.
Description
register address
Read Register Select
Read Only
reserved
Initialize Software
Development Mode
Error-pin Emulation
Mode
reserved
Watchdog Prescaler
Control
reserved
[1]
Rev. 07 — 25 February 2010
01
Value
0
1
1
0
0
1
0
1
0
0
00
01
10
11
11
10
01
00
0
Function
select Special Mode register
read the Interrupt Enable Feedback register
read the Special Mode Feedback register
read the register selected by RRS without writing to the
Special Mode register
read the register selected by RRS and write to the
Special Mode register
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
initialization of software development mode
normal watchdog interrupt, reset monitoring and fail-safe
behavior
pin EN reflects the status of the CANFD bits:
pin EN behaves as an enable pin; see
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
watchdog prescale factor 1
watchdog prescale factor 1.5
watchdog prescale factor 2.5
watchdog prescale factor 3.5
V1 reset threshold = 0.9 × V
V1 reset threshold = 0.7 × V
V1 reset threshold = 0.8 × V
V1 reset threshold = 0.9 × V
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
High-speed CAN/LIN fail-safe system basis chip
EN is set if CANFD = 0000 (no error)
EN is cleared if CANFD is not 0000 (error)
V1(nom)
V1(nom)
V1(nom)
V1(nom)
[2]
UJA1065
© NXP B.V. 2010. All rights reserved.
Section 6.5.2
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